2 EVM Circuit Description

This EVM provides access to the features and measures the performance of the PGA855 device. The PGA855 is equipped with eight binary gain settings, from an attenuating gain of 0.125 V/V to a maximum of 16 V/V, using three digital gain selection pins. By default, the PGA855EVM programmable gain amplifier is configured to a gain of 0.125 V/V. The evaluation board provides shunt jumpers J10, J11, and J12 to set the PGA855 gain.

The device uses two sets of voltage supplies: input stage and output stage. The output-stage power supplies are decoupled from the input stage to limit the PGA855 output-swing voltage level protecting the ADC or downstream device against overdrive damage. The input-stage supplies, VS+ and VS–, are accessible using connector J13. The output-stage supplies, LVDD+ and LVSS–, are accessible using connector J14. Selectable jumpers J9 and J16 set the output-stage supply voltage level equal to the input-stage supplies (default), or to external voltages using connector J14.

The PGA855 incorporates features that simplify interfacing to a fully differential ADC. The output common-mode voltage can be independently set by using the VOCM pin. The VOCM connector sets the output common-mode voltage. If the VOCM connector is not driven, the output common-mode voltage defaults to the PGA855 output stage mid-supply value. The PGA855EVM allows access to the FDA_IN– and FDA_IN+ pins with optional capacitors C4 and C14. These capacitors are in parallel with the PGA855 output-stage internal-feedback resistors to implement noise filtering. Figure 2-1 displays a simplified block diagram of the PGA855EVM. Revision A of the PGA855EVM connects the VOCM voltage divider resistors R1 and R3 to the LVDD+ and LVSS– output-stage supplies. For a full schematic of the PGA855EVM and revision details, see Figure 8-1.

Figure 2-1 PGA855EVM Simplified Schematic