SCAA124 April   2015 RM41L232 , RM42L432 , RM44L520 , RM44L920 , RM46L430 , RM46L440 , RM46L450 , RM46L830 , RM46L840 , RM46L850 , RM46L852 , RM48L530 , RM48L540 , RM48L730 , RM48L740 , RM48L940 , RM48L950 , RM48L952 , RM57L843 , TMS570LC4357 , TMS570LC4357-EP , TMS570LC4357-SEP , TMS570LS0232 , TMS570LS0332 , TMS570LS0432 , TMS570LS0714 , TMS570LS0714-S , TMS570LS0914 , TMS570LS1114 , TMS570LS1115 , TMS570LS1224 , TMS570LS1225 , TMS570LS1227 , TMS570LS2124 , TMS570LS2125 , TMS570LS2134 , TMS570LS2135 , TMS570LS3134 , TMS570LS3135 , TMS570LS3137

 

  1.   Latch-Up
    1.     Trademarks
    2. 1 Introduction
      1. 1.1 What is Latch-Up?
      2. 1.2 Latch-Up Model
      3. 1.3 Mitigating Latch-Up
    3. 2 Latch-Up Testing Methods
      1. 2.1 Latch-Up Standard
      2. 2.2 Current Injection Stress
      3. 2.3 Over-Voltage Stress
      4. 2.4 Signal Latch-Up
      5. 2.5 Analog Product Testing
        1. 2.5.1 Maximum Stress Voltage for Latch-Up (MSV)
        2. 2.5.2 Stressing Special Pins
        3. 2.5.3 High Voltage Testing
    4. 3 References

2.4 Signal Latch-Up

Similar to the Latch-Up description in Section 1.1, that defines a malfunction of the IC, generally, a shorting of the power supply to ground, Signal Latch-Up (sLU) is also a malfunction of the IC; however, a shorting of the signal to ground as opposed to the traditional shorting of the power supply to ground. Latch-Up is detected by a sustained increase in ISUPPLY after the applicable stress is removed. Signal Latch-Up does not manifest itself in a sustained increase in ISUPPLY, but rather detected in a sustained increase in ISIGNAL after the applicable stress in removed. While Latch-Up is generally not a problem associated with normal operation, Signal Latch-Up can be a problem associated with normal operation depending on the signal application. During the design of signal ESD protection structures, there can be intentional SCRs employed that encourage selected parasitic PNPN diodes to trigger under an ESD event. While ESD is an unpowered event, this is not a concern and actually desirable. However, during normal operation since an intentional SCR could exist between a signal pin to ground and the signal pin could be tied or driven to a “hi” state, care must be taken by using design rules on the product to limit effects of Signal Latch-Up, thereby, mitigating the effect of excursion that could trigger the signal ESD SCR and effectively short the signal to ground. If a signal pin is tied or driven to a “lo” state, then the signal voltage is below the ESD SCR holding voltage and signal Latch-Up will not occur.