SCPA070 june 2023 TCAL6408 , TCAL6416 , TCAL9538 , TCAL9539 , TCAL9539-Q1
The interrupt status registers (0x4C and 0x4D) are read only registers used to identify the source of a triggered interrupt. When the interrupt status register is read, a logic 1 designates that the corresponding input pin was the source of the interrupt. A logic 0 indicates that the input pin was not the source of an interrupt.
If a corresponding bit in the interrupt mask register (0x4A and 0x4B) is set to logic 1 (masked), the interrupt state bit returns to logic 0.
For the following example, the TCAL6416 p-port P04 is set to an input and changes from a high to low logic state. Inside the interrupt status register (0x4C) holds the data b00010000 or 0x10 given that the interrupt is not masked. For this example, Bit S-04 = 1 in Table 6-1. Bit S-04 equates to P04 p-port, and the logic 1 indicates that this port set an interrupt because of a change of state on the pin.
BIT | S-07 | S-06 | S-05 | S-04 | S-03 | S-02 | S-01 | S-00 |
Default | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
BIT | S-17 | S-16 | S-15 | S-14 | S-13 | S-12 | S-11 | S-10 |
Default | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
To check for an interrupt on port 1, the interrupt status register internal to the TCAL6416 (or any TCAL I/O expander) needs to be read. First, there needs to be a write to the TCAL6416 using the device address 0x21 followed by a write bit. Then the address of the interrupt status register 0x4C is sent. The next step is to read from the TCAL6416 by sending the device address 0x21 again followed by a read bit. At this point, data from the interrupt status register (0x4C) is read as 0x10 which correctly identifies that P04 interrupt was triggered thus telling us the input change occurred on p-port P04. This entire process is shown in Figure 6-1.