SFFS757 February   2024 DLP4620S-Q1 , DLPC231S-Q1

 

  1.   1
  2. 1Introduction
    1.     Trademarks
  3. 2 DLP4620S-Q1 Chipset Functional Safety Capability
  4. 3Development Process for Management of Systematic Faults
    1. 3.1 TI New-Product Development Process
    2. 3.2 TI Functional Safety Development Process
  5. 4 DLP4620S-Q1 Chipset Overview
    1. 4.1 Targeted Applications
    2. 4.2 DLP4620S-Q1 Chipset Functional Safety Concept
      1. 4.2.1 Typical Hazards
      2. 4.2.2 Chipset Architecture
      3. 4.2.3 Built-In Self Tests
    3. 4.3 Functional Safety Constraints and Assumptions
  6. 5Description of Hardware Component Parts
    1. 5.1 Description of System Level Built In Self Test (BISTs)
  7. 6Management of Random Faults
    1. 6.1 Fault Reporting
      1. 6.1.1 HOST_IRQ
      2. 6.1.2 Error History
      3. 6.1.3 Fault Handling
    2. 6.2 Functional Safety Mechanism Categories
    3. 6.3 Description of Functional Safety Mechanisms
      1. 6.3.1 Video Path Protection
        1. 6.3.1.1 Video Input BISTs
        2. 6.3.1.2 Video Processing BISTs
        3. 6.3.1.3 Video Output BISTs
      2. 6.3.2 Illumination Control Protection
        1. 6.3.2.1 Communication Interface and Register Protection
        2. 6.3.2.2 LED Control Feedback Loop Protection
        3. 6.3.2.3 Data Load and Transfer Protection
        4. 6.3.2.4 Watchdogs and Clock Monitors
        5. 6.3.2.5 Voltage Monitors
  8.   A Summary of Recommended Functional Safety Mechanism Usage
  9.   B Distributed Developments
    1.     B.1 How the Functional Safety Lifecycle Applies to TI Functional Safety Products
    2.     B.2 Activities Performed by Texas Instruments
    3.     B.3 Information Provided
  10.   C Revision History

6.3.1 Video Path Protection

To prevent against corrupted image, the DLP4620S-Q1 chipset includes many Built-In Self Tests (BISTs) that monitor the video path. The BISTs implemented in the chipset monitor and diagnose the input, the processing, and output of the video. An overview of the entire video path with the BISTs is shown in Figure 6-1 below. Further description of the video path and the BISTs is provided in the following sections.

GUID-20240130-SS0I-CMN4-5MDN-QWWSPFS8LL6W-low.svg Figure 6-1 DLP4620S-Q1 Video Path With Diagnostics

Figure 6-2 shows the video path of the DLP4620S-Q1 chipset.

GUID-20240130-SS0I-92LR-MQBX-2ZRWPHRDFXSK-low.svg Figure 6-2 DLP4620S-Q1 Video Path

The DLPC231S-Q1 can use several display sources. Source video can come from a vehicle's GPU, either using OpenLDI or Parallel RGB, Internal Test Patterns, or Splash Images. The video source is selected by a host MCU.

After the input multiplexer, some general video processing is applied to the video. This processing includes scaling, and color space correction (for some splash images). Next, some DMD specific video processing is applied. This includes de-gamma correction, dithering, and finally, a conversion to single color "bit plane" data.

"Bit Planes" are sub-frames corresponding to single color codes. The DMD displays single color sub-frames and the human eye integrates them to form a full color image for that frame of the video. After conversion from standard video to bit planes the video is sent to the FMT block.

The FMT consists of some video processing logic and is connected to two frame buffers. The processing in the FMT and the use of the frame buffers is explained below:

  • Performs flips, crops, and bezel adjustment of the video. This video is stored into one of the two frame buffers.
  • Simultaneously, video from the other frame buffer is output to the DMD.
  • The two frame buffers switch roles every frame.

The DMD High Speed Interface is used to load time multiplexed binary data into the DMD's Memory Array. This binary data determines the state of each DMD mirror during each "bit plane". A reset pulse transitions micro-mirrors from one "bit plane" to the next. The DLPC231S-Q1 utilizes a low speed interface that is used for configuration of DMD registers, generating the DMD mirror reset waveforms, and monitoring the DMD.

The DLP4620S-Q1 chipset contains overlapping BIST coverage of the various blocks involved in the video path. These BISTs cover the input, processing, and output of the video path. These BISTs are discussed in the following sections.