SFFS757 February   2024 DLP4620S-Q1 , DLPC231S-Q1

 

  1.   1
  2. 1Introduction
    1.     Trademarks
  3. 2 DLP4620S-Q1 Chipset Functional Safety Capability
  4. 3Development Process for Management of Systematic Faults
    1. 3.1 TI New-Product Development Process
    2. 3.2 TI Functional Safety Development Process
  5. 4 DLP4620S-Q1 Chipset Overview
    1. 4.1 Targeted Applications
    2. 4.2 DLP4620S-Q1 Chipset Functional Safety Concept
      1. 4.2.1 Typical Hazards
      2. 4.2.2 Chipset Architecture
      3. 4.2.3 Built-In Self Tests
    3. 4.3 Functional Safety Constraints and Assumptions
  6. 5Description of Hardware Component Parts
    1. 5.1 Description of System Level Built In Self Test (BISTs)
  7. 6Management of Random Faults
    1. 6.1 Fault Reporting
      1. 6.1.1 HOST_IRQ
      2. 6.1.2 Error History
      3. 6.1.3 Fault Handling
    2. 6.2 Functional Safety Mechanism Categories
    3. 6.3 Description of Functional Safety Mechanisms
      1. 6.3.1 Video Path Protection
        1. 6.3.1.1 Video Input BISTs
        2. 6.3.1.2 Video Processing BISTs
        3. 6.3.1.3 Video Output BISTs
      2. 6.3.2 Illumination Control Protection
        1. 6.3.2.1 Communication Interface and Register Protection
        2. 6.3.2.2 LED Control Feedback Loop Protection
        3. 6.3.2.3 Data Load and Transfer Protection
        4. 6.3.2.4 Watchdogs and Clock Monitors
        5. 6.3.2.5 Voltage Monitors
  8.   A Summary of Recommended Functional Safety Mechanism Usage
  9.   B Distributed Developments
    1.     B.1 How the Functional Safety Lifecycle Applies to TI Functional Safety Products
    2.     B.2 Activities Performed by Texas Instruments
    3.     B.3 Information Provided
  10.   C Revision History

5.1 Description of System Level Built In Self Test (BISTs)

In order to integrate and evaluate this chipset into an ISO26262 certified system, TI recommends validating BIST functionality in-system. Recommended methods for testing each BIST are listed in Table 5-4. For cases that require batch command sets or special software builds to induce failures, please contact TI.

Table 5-4 Recommended Methods for Testing BISTs
BIST Method to Induce Failure Related HOST SPI Command
DLPC231S-Q1 Host Command CRC Send SPI command to DLPC231S-Q1 with incorrect CRC 51h
Video Source Loss Detection Remove video source N/A
Video Tell-Tale Checksum Use one of the following methods:
  1. Modify source without changing expected checksum
  2. Change expected checksum
  3. Change checksum check region
 2Bh / 2Ch
Video Frame Counter Checksum Use one of the following methods:
  1. Modify source to change frame counter
  2. Change frame count check region
 2Bh / 2Ch
Average Picture Level
  1. Set input image to full white
  2. Set APL level to 100
 2Fh / 30h
Loss of Dimming Command Enable test then do not send any dimming commands 33h / 34h
Photo Feedback Monitor Disconnect photo-diode on system N/A
DLPC231S-Q1 Processor Memory ECC This failure can only be induced by TI. Please contact TI for more information. N/A
Flash Table Transport CRC Software build required to induce failure. Please contact TI N/A
Frame Buffer Swap Watchdog Batch command set required to induce failure. Please contact TI N/A
Sequencer Instruction Read Watchdog Batch command set required to induce failure. Please contact TI N/A
DMD Reset Instruction Watchdog Batch command set required to induce failure. Please contact TI N/A
DLPC231S-Q1 System Voltage Monitor Build and program flash with modified VMAIN threshold
OR
Adjust VMAIN with hardware until error is detected		 N/A
DLPC231S-Q1 DMD Voltage Monitor Software build required to induce failure. Please contact TI N/A
DMD Clock Monitor No method for inducing this error. TI performed validation on this test
DMD High Speed Interface Training Build and program flash image with incorrect pin mapping. Set system to display mode. N/A
DMD Low Speed Interface Test Software build required to induce failure. Please contact TI N/A
TPS99000S-Q1 DLPC231S-Q1 Processor Watchdog (WD1) Batch command set required to induce failure. Please contact TI N/A
TPS99000S-Q1 DLPC231S-Q1 Sequencer Watchdog (WD2) Batch command set required to induce failure. Please contact TI N/A
TPS99000S-Q1 Clock Ratio Monitor Software build required to induce failure. Please contact TI N/A
TPS99000S-Q1 Register checksum Batch command set required to induce failure. Please contact TI N/A
DLPC231S-Q1 Front-End Functional Test Software build required to induce failure. Please contact TI N/A
DLPC231S-Q1 Back-End Functional Test Software build required to induce failure. Please contact TI N/A
DLPC231S-Q1 Memory BISTs Software build required to induce failure. Please contact TI N/A
TPS99000S-Q1 Signal Interface Disconnect DLPC231S-Q1 to TPS99000S-Q1 SPI or LED Select Interface N/A
DMD Memory Test No method for inducing this error. TI performed validation on this test N/A
Flash Data Verification Software build required to induce failure. Please contact TI N/A
DLPC231S-Q1 Boot ROM CRC Software build required to induce failure. Please contact TI N/A
DLPC231S-Q1 Flash Table CRC Software build required to induce failure. Please contact TI N/A
DLPC231S-Q1 Main App CRC Software build required to induce failure. Please contact TI N/A
DLPC231S-Q1 to TPS99000S-Q1 SPI Byte-Wise Parity No method for inducing persistent parity error. TI performed software verification on this test N/A
DLPC231S-Q1 to TPS99000S-Q1 ADC Interface SPI Parity No method for inducing persistent parity error. TI performed software verification on this test N/A
TPS99000S-Q1 password protected register space No method for inducing this error N/A
DAC to ADC loopback test Disconnect DLPC231S-Q1 to TPS99000S-Q1 SPI N/A