SLAAE64 may   2023 AFE58JD48 , DAC81001 , DAC8801 , DAC8830 , OPA2210 , REF5010 , REF5040 , THS4130

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Proposed Topologies
    1. 2.1 Proposal 1: Using R-2R DAC (DAC8830)
      1. 2.1.1 Highlighted Products
        1. 2.1.1.1 DAC8830
        2. 2.1.1.2 OPA2210
        3. 2.1.1.3 THS4130
        4. 2.1.1.4 REF5040
      2. 2.1.2 Design Circuit
      3. 2.1.3 PSpice-TI Simulation
    2. 2.2 Proposal 2: Using M-DAC (DAC8801)
      1. 2.2.1 Highlighted Products
        1. 2.2.1.1 DAC8801
        2. 2.2.1.2 OPA2210
        3. 2.2.1.3 THS4130
        4. 2.2.1.4 REF5010
      2. 2.2.2 Design Circuit
      3. 2.2.3 PSpice-TI Simulation
    3. 2.3 Proposal 3: Using Low-Noise R-2R DAC (DAC81001)
      1. 2.3.1 Highlighted Products
        1. 2.3.1.1 DAC81001
        2. 2.3.1.2 OPA2210
        3. 2.3.1.3 THS4130
        4. 2.3.1.4 REF5010
      2. 2.3.2 Design Circuit
      3. 2.3.3 PSpice-TI Simulation
  6. 3Conclusion
  7. 4References

2.2.2 Design Circuit

This section recommends another approach for a TGC control circuit with a multiplying DAC (MDAC) to generate the drive for VCNTL. Figure 2-5 shows a high-level block diagram of this topology. Even though the VCNTL range is from –0.4 V to 0.4 V, a much higher reference voltage, VREF = 10 V, is used for the DAC. Filtering the reference voltage removes high-frequency noise and the DAC generates an output range of 0 to VREF. The output of the DAC is buffered using an op amp to a level of –VREF to 0. Additional signal conditioning can involve low-pass filtering to reduce the noise bandwidth. Finally, an attenuation circuit reduces the range to the desired VCNTL range using a R-2R-DAC to generate the drive for VCNTL.


GUID-20221116-SS0I-5X9R-WLCP-MVBHKDHBNTDG-low.svg

Figure 2-5 A Current-Output MDAC is Used in Generating a TGC Signal

The previous approach that starts off with a high-reference voltage and high DAC full-scale range, followed by attenuation, helps attenuate noise contributions from the reference circuit and the DAC, as well as other op amps used for signal conditioning. Using this topology, Figure 2-6 shows the drive circuit for the control voltage.


GUID-20221116-SS0I-KQLQ-X6KR-WCTPJGKQNLGG-low.svg

Figure 2-6 Proposal 2 VCNTL Drive Circuit

The REF5010 generates a 10-V reference voltage that is filtered and buffered to generate VREF_10V. This serves as the reference voltage for the DAC8801, which generates a current output on IOUT corresponding to the digital input code. The IOUT pin of the DAC8801 is connected to the virtual ground (negative terminal) of the OPA2210; the feedback resistor (RFB is internal to the DAC8801) is connected to the output of the OPA2210, resulting in a current-to-voltage conversion. The output of the OPA2210 has a range of –10 V to 0 V and it is input to the THS4130, which is configured as a Sallen-Key filter. Finally, the 10-V range is attenuated down to a –0.4-V to 0.4-V range, with a common mode of 1.3 V using a resistive attenuator.