SLAAE64 may   2023 AFE58JD48 , DAC81001 , DAC8801 , DAC8830 , OPA2210 , REF5010 , REF5040 , THS4130

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Proposed Topologies
    1. 2.1 Proposal 1: Using R-2R DAC (DAC8830)
      1. 2.1.1 Highlighted Products
        1. 2.1.1.1 DAC8830
        2. 2.1.1.2 OPA2210
        3. 2.1.1.3 THS4130
        4. 2.1.1.4 REF5040
      2. 2.1.2 Design Circuit
      3. 2.1.3 PSpice-TI Simulation
    2. 2.2 Proposal 2: Using M-DAC (DAC8801)
      1. 2.2.1 Highlighted Products
        1. 2.2.1.1 DAC8801
        2. 2.2.1.2 OPA2210
        3. 2.2.1.3 THS4130
        4. 2.2.1.4 REF5010
      2. 2.2.2 Design Circuit
      3. 2.2.3 PSpice-TI Simulation
    3. 2.3 Proposal 3: Using Low-Noise R-2R DAC (DAC81001)
      1. 2.3.1 Highlighted Products
        1. 2.3.1.1 DAC81001
        2. 2.3.1.2 OPA2210
        3. 2.3.1.3 THS4130
        4. 2.3.1.4 REF5010
      2. 2.3.2 Design Circuit
      3. 2.3.3 PSpice-TI Simulation
  6. 3Conclusion
  7. 4References

Abstract

TI's low-noise analog front ends (AFE) have a time gain control (TGC) feature that helps achieve the best possible signal-to-noise ratio (SNR) for ultrasound applications. This application note describes the specifications and design considerations of a circuit used for generating a time-varying VCNTL to drive multiple AFE receiver chips. The document discusses three different proposals to achieve noise performance. Also included is a detailed description of the circuits and how PSPICE simulations can be used for noise analysis.