4 Determination of Incoming Timing in Auto-Detected Mode

It is also possible to detect the incoming timings by reading certain status registers. The FSYNC Rate and the BCLK to FSYNC ratio of the Primary and Secondary ASI can be monitored with the registers.

1. PASI_SAMP_RATE_STS (B0_P0_R62_D[7:2])
   • Detected Primary FSYNC Rate
2. PLL_MODE_STS (B0_P0_R62_D[1:0])
   • Derived PLL mode of operation

   PLL usage status.

   0d = PLL used in integer mode

   1d = PLL used in fractional mode

   2d = PLL not used

   3d = Reserved

3. SASI_SAMP_RATE_STS (B0_P0_R63_D[7:2])
   • Detected Secondary FSYNC Rate
4. DEM_RATE_STS (B0_P0_R64_D[7:6])
   • Derived DEM configurations

   DEM rate usage status.

   0d = 1x DEM used for ADC and DAC modulators

   1d = 2x DEM used for ADC and DAC modulators

   2d = 4x DEM used for ADC and DAC modulators

   3d = programmed value of DEM rate used for ADC and DAC modulators

5. FS_CLKSRC_RATIO_DET_MSB_STS (B0_P0_R64_D[5:0])
   • Audio clock source clock to FSYNC ratio detected
6. FS_CLKSRC_RATIO_DET_LSB_STS (B0_P0_R65_D[7:0])
   • Audio clock source clock to FSYNC ratio detected