3 Detection of Clock Errors

When FSYNC Rate changes or the Ratio between Clock and FSYNC changes a clock error is generated. A corresponding active low reset to the Clock Detect Core Block are generated which are mapped to respective Fs Rate detection and Ratio Detection logics.

1. DSP_CLK_ERR (B0_P0_R60_D7)
   • 1 when DSP fails to derive the clock tree settings w.r.t the provided configurations (Only can occur when PLL fractional mode is not supported)
2. MIPS_INSUFF_ERR (B0_P0_R60_D6)
   • 1 when DSP is able to derive the clock tree settings but the MIPS are insufficient for the requested processing (Only can occur when PLL fractional mode is not supported)
3. DEM_RATE_ERR (B0_P0_R60_D3)
   • 1 when Requested DEM configurations are not possible to support
4. PDM_CLK_ERR (B0_P0_R60_D2)
   • 1 when Requested PDM clock is not possible to support
5. PASI_BCLK_FS_RATIO_ERR (B0_P0_R61_D7)
   • 1 when a change in Primary BCLK to FSYNC Ratio is detected
6. SASI_BCLK_FS_RATIO_ERR (B0_P0_R61_D6)
   • 1 when a change in Secondary BCLK to FSYNC Ratio is detected
7. CCLK_FS_RATIO_ERR (B0_P0_R61_D5)
   • 1 when a change in CCLK to FSYNC Ratio is detected
8. PASI_FS_ERR (B0_P0_R61_D4)
   • 1 when a change in Primary FSYNC Rate is detected
9. SASI_FS_ERR (B0_P0_R61_D3)
   • 1 when a change in Secondary FSYNC Rate is detected