SLDU019B December   2015  – March 2016 PGA450-Q1

 

  1.   PGA450Q1EVM-S User's Guide and TIDA-00151 UART Demo Instructional
    1.     Trademarks
    2. 1 Introduction
    3. 2 Setup and Operation
      1. 2.1 Input and Output Connectors
      2. 2.2 Basic Operation
        1. 2.2.1 Programming the PGA450-Q1 DEVRAM or OTP Memory
        2. 2.2.2 Programming the PGA450-Q1 EEPROM
        3. 2.2.3 Testing the UART Connection With the TI GER Board
      3. 2.3 UART Command Listing
    4. 3 Software
      1. 3.1 IDE Output File Configuration
        1. 3.1.1 Setup for DEVRAM Output File
        2. 3.1.2 Setup for OTP Output File
      2. 3.2 Interface Descriptions
        1. 3.2.1 UART Interface
        2. 3.2.2 LIN Interface
        3. 3.2.3 Serial-Peripheral Interface
    5. 4 Schematic, Bill of Materials, and Layout
      1. 4.1 Schematic
      2. 4.2 Bill of Materials
        1. 4.2.1 BOM
      3. 4.3 Board Layout and Component Placement
    6. 5 References
  2.   Revision History

2.2.1 Programming the PGA450-Q1 DEVRAM or OTP Memory

The PGA450Q1EVM-S memory is preprogrammed to operate from OTP memory, meaning that the PGA450-Q1 device is permanently programmed with a set of predefined commands as described in Section 2.3. If the user prefers to customize or modify the firmware for different commands, the PGA450-Q1 device must be replaced with a pristine PGA450-Q1 device, and follow the instructions provided in this section. Go to Section 2.3 if the device will not be replaced. Use the steps that follow to program the device for DEVRAM or OTP memory.

  1. Connect a 12-V system supply voltage to the EVM at J2-1 (MAIN) and connect the SPI pins of the EVM at J3 to the SPI pins on the TI GER board.
    2. tiger_board_sldu019.gifFigure 2. TI GER Board SPI and UART Connections

    Table 2. TI GER to PGA450Q1EVM-S Connections

    Connection TI-GER Pin EVM Pin
    SPI-MISO 1 J3-1 (SDO)
    SPI-SCLK 3 J3-3 (SCLK)
    SPI-CS 5 J3-4 (CS)
    SPI-MOSI 7 J3-2 (SDI)
    UART-TXD 10 J4-3 (RXD)
    UART-RXD 20 J4-4 (TXD)
    GND 4 J2-4 (GND)
  2. Connect the TI GER board to the PC.
  3. Open the PGA450Q1EVM GUI.
  4. Click the OFF (Micro Reset) button on the ESFR tab.
  5. Click the READ ALL button to read all registers on the ESFR tab. Use register B4 (TEMP_SENS) as an indicator to ensure the device is operating and communicating properly through SPI. Proper communication can be verified if the data of the register reads a value other than 0x00 or 0xFF.
  6. Under the OTP tab, click Check OTP Status button. If the PGA450-Q1 device has not been previously been OTP programmed, the status displays OTP Empty.
  7. Connect the 8-V supply to the VPROG_OTP pin on the sensor to program the OTP memory, to program the DEVRAM memory for the first time, or if the OTP status displays OTP Empty.
  8. If programming DEVRAM memory, go to the DEVRAM tab. For a pristine IC that has never been programmed (OTP status displays OTP Empty), check the Program OTP Memory Also box for the GUI. This option programs both the OTP and DEVRAM memory. The OTP memory will be programmed with a long-jump statement to redirect the firmware to load into and be run from the DEVRAM memory. If programming OTP memory for production release or a permanently coded PGA450-Q1 device, go to the OTP tab, click Load .HEX File into GUI, and locate the appropriate OTP-based .HEX file.
  9. Programming and verification of the device occurs automatically.
  10. When the device is verified, disconnect the VPROG_OTP supply voltage (if applicable). Do not disconnect system supply voltage if DEVRAM has been programmed, because the DEVRAM memory will clear when the PGA450-Q1 device is power cycled.