The TPS40100EVM-100 has the ability to be synchronized to an external clock. To begin testing, set up the EVM according to Figure 5-2. Connector J1 contains both the power-good pin and sync-in pin. Power good can be monitored for its steady state response with a DMM or with an oscilloscope to illustrate its dynamic response. The power-good voltage swing will range from 0 V– 4.5 V depending on the condition of the output. A low on this pin dictates a power fault and a high (4.5 V) conveys “power ok.”

Pin 4 of J1 is the input for an external clock frequency. To test, set up a function generator to provide a squarewave at a frequency of above 410 kHz and below 480 kHz. The function generator should be set to provide a 0-V to 5-V square wave with a 50% duty cycle. Once power is applied to the EVM, apply the external clock to the sync-in pin and observe the gate drive of the low-side MOSFET (Q2). This should be measured using an oscilloscope measuring at TP7. Gate drive pulse will coincide with external clock frequency. Please see Figure 5-12.