1 Introduction

An ESD event rapidly forces current (see Figure 1-1), I_ESD , into a system, usually through a user interface such as a cable connection, or a human input device like a key on a keyboard. Protecting a system against ESD using a TVS relies upon the TVS being able to shunt I_ESD to ground. Optimizing a PCB Layout for ESD suppression is largely dependant on designing the path to ground for I_ESD with as little impedance as possible. During an ESD event, the voltage presented to the protected integrated circuit (Protected IC), V_ESD, is a function of I_ESD and the impedance presented to it. Since the designer has no control over I_ESD, lowering the impedance to ground is the primary means available for minimizing V_ESD.

Lowering the impedance presents several challenges. Mainly, it cannot be of zero impedance, or the signal line being protected would be shorted to ground. In order for the circuit to have a realistic application, the protected line needs to be able to maintain some voltage, usually under a high impedance to ground. This is where the TVS becomes applicableLowering the impedance presents several challenges. Mainly, it cannot be of zero impedance, or the signal line being protected would be shorted to ground. In order for the circuit to have a realistic application, the protected line needs to be able to maintain some voltage, usually under a high impedance to ground. This is where the TVS becomes applicable

A TVS is an array of diodes (see Figure 1-2 for a typical example) arranged to present a very high impedance to the voltages normally present in the circuit, but if voltages exceed the design, the TVS diodes will breakdown and shunt I_ESD to ground before it can damage the system being protected. The system designer is then challenged to lower the impedance for I_ESD from the ESD Source through the TVS to ground.

The impedance presented to I_ESD is a function of any impedance inherent with the TVS (in the diode array and the package of the TVS) and the PCB Layout between the ESD Source and the TVS ground. A TVS is generally designed to offer as low of an impedance to ground for I_ESD as its overall design constraints will allow. With the proper TVS selected, a critical phase of the design is to lower the impedance in the PCB Layout between the ESD Source and the TVS ground.

Another concern created by the rapidly changing I_ESD is its associated rapidly changing electromagnetic field (EM) causing interference (EMI) to couple onto other circuits of the PCB. This is especially true in the area between the ESD Source and the TVS. Once the TVS shunts I_ESD to ground, the trace between the TVS and the Protected IC should be relatively free of EMI. Therefore, unprotected circuits should not be adjacent to an ESD protected circuit's traces between the ESD Source and the TVS. In order to keep EMI emissions at a minimum, circuit traces between the ESD Source and the TVS should have corners which do not exceed 45° or, ideally, which are curved with large radii.

In today's PCB Layout, board space is at a premium. ICs, including TVSs, are designed to be very compact. Also, the density of their placement on the PCB is continually increasing. Multiple layer PCB boards and routing lean heavily upon VIAs for maximizing the density to increase the system's feature set while decreasing the system's size. This PCB architecture, particularly related to layer switching and VIAs, plays an important role in shunting I_ESD to ground through the TVS. Large differences in V_ESD at the Protected IC can be induced by the manner in which the circuit is routed to the TVS using VIAs. Generally, placing a VIA between the ESD Source and the TVS is detrimental, but in some circumstances the designer is forced to do so. Even in these circumstance, if properly done, V_ESD can still be minimized at the Protected IC.

Grounding schemes are critical in protecting against ESD. Having a chassis ground for the TVS that is separated from the digital and/or analog ground by inductance provides very good protection against ESD related failures. Yet it presents great challenges when routing high speed circuits across multiple ground planes. For this reason, many designs use one common ground for the protected circuits. Ground planes are necessary for the TVS to have success in dissipating I_ESD without increasing V_ESD. Electrical connections to an earth grounded chassis, like a PCB grounded through-hole for a chassis screw, immediately adjacent to the TVS ground and the ESD Source's ground (for example, a connector shield) provide a sound methodology in keeping ground shifts at Protected ICs to a minimum. If a system cannot utilize a chassis earth ground, tightly coupled multiple layer ground planes can help keep ground shifts at Protected ICs to a minimum.

To summarize these parameters, successfully protecting a system against ESD includes:

• Controlling impedances around the TVS for dissipating ESD current, I_ESD
• Limiting the effects of EMI on unprotected circuits
• Properly using VIAs to maximize ESD dissipation by the TVS
• Designing a grounding scheme which has very low impedance for the TVS