SLVAFQ2 December   2023 TPS65219

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Power Delivery Networks (PDNs)
    1. 2.1 TPS652190C Power Rails Configuration
    2. 2.2 LP87334F Power Rails Configuration
    3. 2.3 Powering i.MX 8M Plus and DDR4
    4. 2.4 Powering i.MX 8M Plus and LDDR4
    5. 2.5 PMICs Digital Configuration
    6. 2.6 Power-Up Sequence
    7. 2.7 Power-Down Sequence
  6. 3Supporting i.MX 8M Plus Low Power Modes
  7. 4PMIC Schematic Example
  8. 5TPS6521905 User-Programmable Version
  9. 6Summary
  10. 7References

2.2 LP87334F Power Rails Configuration

  • Buck1 and Buck2 are configured in multi-phase to support higher current required for VDD_SOC. This PMIC rail supplies SoC logic, DRAM controller, GPU, and VPU controllers (VDD_SOC, VDD_VPU, VDD_GPU, VDD_DRAM).
  • LDO1 and LDO2 are used for peripherals. They are configured to output 2.5V and can be used to supply the VPP rail of the DDR4 memory and the 2.5V rail of the Ethernet PHY.
Note: For a detailed description of the default TPS652190C register settings, refer to the Technical Reference Manual SNVU881
Table 2-1 Power Delivery Networks (PDNs)
PMIC Memory Type Power Delivery Network (PDN)
TPS652190C + LP87334F DDR4 Section 2.3
TPS65219xx + 0.85V discrete Buck LPDDR4 Section 2.4
TPS6521905 user-programmable PMIC Any Section 5