SLVU579A December   2011  – September 2021 TPS54427

 

  1.   Trademarks
  2. 1Introduction
  3. 2Performance Specification Summary
  4. 3Modifications
    1. 3.1 Output Voltage Setpoint
    2. 3.2 Output Filter and Closed-Loop Response
  5. 4Test Setup and Results
    1. 4.1 Input/Output Connections
    2. 4.2 Start-Up Procedure
    3. 4.3 Efficiency
    4. 4.4 Load Regulation
    5. 4.5 Line Regulation
    6. 4.6 Load Transient Response
    7. 4.7 Output Voltage Ripple
    8. 4.8 Input Voltage Ripple
    9. 4.9 Start-Up and Shut-Down
  6. 5Board Layout
    1. 5.1 Layout
  7. 6Schematic, Bill of Materials, and Reference
    1. 6.1 Schematic
    2. 6.2 Bill of Materials
    3. 6.3 Reference
  8. 7Revision History

Layout

The board layout for the TPS54427 is shown in Figure 5-1 through Figure 5-5. The top layer contains the main power traces for VIN, VOUT, and ground. Also on the top layer are connections for the pins of the TPS54427 and a large area filled with ground. Many of the signal traces also are located on the top side. The input decoupling capacitors are located as close to the IC as possible. The input and output connectors, test points, and all of the components are located on the top side. An analog ground (GND) area is provided on the top side. Analog ground (GND) and power ground (PGND) are connected at a single point on the top layer near C6. The bottom layer is primarily power ground but also has a trace to connect VIN to the enable jumper, a trace to connect VREG5 to TP5, and the feedback trace from VOUT to the voltage setpoint divider network.

GUID-4314B3F0-5AD2-447F-ADFC-C1A850F21BC1-low.gifFigure 5-1 Top Assembly
GUID-ABCE5BCA-DCA7-4DC0-A661-A44F3167015A-low.gifFigure 5-2 Top Layer
GUID-1186C8DC-BD79-4354-B145-46035847F18C-low.gifFigure 5-3 Internal Layer 1
GUID-7C76F09C-9F2A-4F92-9175-2E7558EECE9A-low.gifFigure 5-4 Internal Layer 2
GUID-2CAD2B84-DF29-44FA-B7CB-28AB3DD15301-low.gifFigure 5-5 Bottom Layer