SLWU095 april   2023

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Functionality
    1. 2.1 ADC EVM Data Capture
    2. 2.2 DAC EVM Pattern Generator
  5. 3Hardware Configuration
    1. 3.1 Power Connections
    2. 3.2 Switches, Jumpers, and LEDs
      1. 3.2.1 Switches and Push-Buttons
      2. 3.2.2 Jumpers
    3. 3.3 LEDs
      1. 3.3.1 Power and Configuration LEDs
      2. 3.3.2 Spare LEDs
      3. 3.3.3 Connectors
        1. 3.3.3.1 SMA Connectors
        2. 3.3.3.2 FPGA Mezzanine Card (FMC+) Connector
        3. 3.3.3.3 JTAG Connectors
        4. 3.3.3.4 USB3.0 I/O Connection
  6. 4Software Start-Up
    1. 4.1 Installation Instructions
    2. 4.2 USB Interface and Drivers
  7. 5Downloading Firmware

3.3.3.2 FPGA Mezzanine Card (FMC+) Connector

The TSW14J59 EVM has one connector to allow for the direct plug in of TI JESD204C_B serial interface ADC and DAC EVMs. The specifications for this connector are mostly derived from the ANSI/VITA 57.4 FPGA Mezzanine Card (FMC+) Standard. This standard describes the compliance requirements for a low-overhead protocol bridge between the IO of a mezzanine card and an FPGA processing device on a carrier card. This specification is being used by FPGA vendors on their development platforms.

The FMC+ connector, J3, provides the interface between the TSW14J59EVM and the ADC or DAC EVM under test. This 560-pin Samtec high-speed, high-density connector (part number ASP-184329-01) is an excellent choice for high-speed differential pairs up to 32.5 Gbps.

In addition to the JESD204B/C standard signals, several CMOS single-ended signals and LVDS differential signals are connected between the FMC+ and FPGA. These signals can allow the HSDC Pro GUI to control the SPI serial programming of ADC and DAC EVMs that support this feature. The connector pinout description is shown in Table 3-5.

Table 3-5 FMC+ Connector Description of the TSW14J59
FMC+ Signal NameFMC+ PinStandard JESD204 Application MappingDescription
DP0_RX_P/NC6 and C7Lane 0± (M → C)JESD Serial data transmitted from mezzanine and received by carrier
DP1_RX_P/NA2 and A3Lane 1± (M → C)JESD Serial data transmitted from mezzanine and received by carrier
DP2_RX_P/NA6 and A7Lane 2± (M → C)JESD Serial data transmitted from mezzanine and received by carrier
DP3_RX_P/NA10 and A11Lane 3± (M → C)JESD Serial data transmitted from mezzanine and received by carrier
DP4_RX_P/NA14 and A15Lane 4± (M → C)JESD Serial data transmitted from mezzanine and received by carrier
DP5_RX_P/NA18 and A19Lane 5± (M → C)JESD Serial data transmitted from mezzanine and received by carrier
DP6_RX_P/NB16 and B17Lane 6± (M → C)JESD Serial data transmitted from mezzanine and received by carrier
DP7_RX_P/NB12 and B13Lane 7± (M → C)JESD Serial data transmitted from mezzanine and received by carrier
DP8_RX_P/NB8 and B9Lane 8± (M → C)JESD Serial data transmitted from mezzanine and received by carrier
DP9_RX_P/NB4 and B5Lane 9± (M → C)JESD Serial data transmitted from mezzanine and received by carrier
DP10_RX_P/NY10 and Y11Lane 10± (M → C)JESD Serial data transmitted from mezzanine and received by carrier
DP11_RX_P/NZ12 and Z13Lane 11± (M → C)JESD Serial data transmitted from mezzanine and received by carrier
DP12_RX_P/NY14 and Y15Lane 12± (M → C)JESD Serial data transmitted from mezzanine and received by carrier
DP13_RX_P/NZ16 and Z17Lane 13± (M → C)JESD Serial data transmitted from mezzanine and received by carrier
DP14_RX_P/NY18 and Y19Lane 14± (M → C)JESD Serial data transmitted from mezzanine and received by carrier
DP15_RX_P/NY22 and Y23Lane 15± (M → C)JESD Serial data transmitted from mezzanine and received by carrier
DP0_TX_P/NC2 and C3Lane 0± (C → M)JESD Serial data transmitted from carrier and received by mezzanine
DP1_TX_P/NA22 and A23Lane 1± (C → M)JESD Serial data transmitted from carrier and received by mezzanine
DP2_TX_P/NA26 and A27Lane 2± (C → M)JESD Serial data transmitted from carrier and received by mezzanine
DP3_TX_P/NA30 and A31Lane 3± (C → M)JESD Serial data transmitted from carrier and received by mezzanine
DP4_TX_P/NA34 and A35Lane 4± (C → M)JESD Serial data transmitted from carrier and received by mezzanine
DP5_TX_P/NA38 and A39Lane 5± (C → M)JESD Serial data transmitted from carrier and received by mezzanine
DP6_TX_P/NB36 and B37Lane 6± (C → M)JESD Serial data transmitted from carrier and received by mezzanine
DP7_TX_P/NB32 and B33Lane 7± (C → M)JESD Serial data transmitted from carrier and received by mezzanine
DP8_TX_P/NB28 and B29Lane 8± (C → M)JESD Serial data transmitted from carrier and received by mezzanine
DP9_TX_P/NB24 and B25Lane 9± (C → M)JESD Serial data transmitted from carrier and received by mezzanine
DP10_TX_P/NZ24 and Z25Lane 10± (C → M)JESD Serial data transmitted from carrier and received by mezzanine
DP11_TX_P/NY26 and Y27Lane 11± (C → M)JESD Serial data transmitted from carrier and received by mezzanine
DP12_TX_P/NZ28 and Z29Lane 12± (C → M)JESD Serial data transmitted from carrier and received by mezzanine
DP13_TX_P/NY30 and Y31Lane 13± (C → M)JESD Serial data transmitted from carrier and received by mezzanine
DP20_TX_P/NZ8 and Z9Lane 14± (C → M)JESD Serial data transmitted from carrier and received by mezzanine
DP21_TX_P/NY6 and Y7Lane 15± (C → M)JESD Serial data transmitted from carrier and received by mezzanine
GBTCLK0_M2C_P/ND4 and D5DEVCLKA± (M → C)Primary carrier-bound reference clock required for FPGA giga-bit transceivers. Equivalent to device clock.
GBTCLK1_M2C_P/NB20 and B21Alt. DEVCLKA± (M → C)Alternate Primary Carrier-bound reference clock required for FPGA giga-bit transceivers. For use when DEVCLKA (M → C) is not available
Device Clock, SYSREF, and SYNC
CORE_CLK_P/NG6 and G7DEVCLKB± (M → C)Secondary carrier-bound device clock. Used for special FPGA functions such as sampling SYSREF
SYSREFP/NG9 and G10SYSREF± (M → C)Carrier-bound SYSREF signal
SYNCB_INH31SYNCCarrier-bound SYNC signal
SYNCB_OUTH32SYNCMezzanine-bound SYNC signal
AFE_SYNCOUTF10

AFE

DAC SYNC		Carrier-bound SYNC signal for use in class 0/1/2 JESD204B systems
Special Purpose I/O
GPIO_G12/G13G12 and G13Spare IO from FPGA pins AA13 and Y13. Enabled with jumper J42 removed
SPIO_SCLKG31Spare SPI SCLK from FPGA pin
GPIO_H25H25Spare IO from FPGA pin AF15. Enabled with jumper J42 removed
GPIO_H26H26Spare IO from FPGA pin AF14. Enabled with jumper J42 removed
GPIO_H28H28Spare IO from FPGA pin AF13. Enabled with jumper J42 removed
GPIO_H29H29Spare IO from FPGA pin AE13. Enabled with jumper J42 removed
SPIO_CSB_0H34Spare SPI chip select from FPGA pin Y15
SPIO_CSB_1H35Spare SPI chip select from FPGA pin

Y16

SPIO_CSB_2H37Spare SPI chip select from FPGA pin

H14

SPIO_CSB_3H38Spare SPI chip select from FPGA pin

J14

PRSNT_M2C_LH2PresentI2C input. Indicates if a mezzanine card is present
SPI1_SCLKD26SPI clock from FPGA pin J15
SPI1_CSBD27SPI chip select from FPGA pin G12
HSPC_PRSNT_M2C_LZ1PresentI2C input. Indicates if a mezzanine card is present.
SPI1_SDIO_0C26Spare from FPGA pin

W15

SPI1_SDIO_1C27Spare from FPGA pin

W16

FMC_I2C_SCLC30Spare USB2.0 I/F
FMC_I2C_SDAC31Spare USB2.0 I/F
GPIO_G27/G28G27, G28Spare IO from FPGA pins W13 and W12. Enabled with jumper J42 removed
GPIO30G30Spare IO from FPGA pin AD14
SPI0_SDIO_0G33Spare SPI data I/O from FPGA pin AD13
SPI0_SDIO_1G34Spare SPI data I/O from FPGA pin AC14
SPI0_SDIO_2G36Spare SPI data I/O from FPGA pin AC13
SPI0_SDIO_3G37Spare SPI data I/O from FPGA pin AA15
12P0VC35, C37, L36, L37, L4012 V output supply
3P3VC39, D32, D36, D38, D40, Z403.3V output supply
VADJE39, G39, H40, F40Adjustable output supply. Default set to 1.8V.