SNLA261A August 2016 – March 2024 DP83822H , DP83822HF , DP83822I , DP83822IF , DP83825I , DP83826E , DP83826I , DP83867CR , DP83867CS , DP83867E , DP83867IR , DP83867IS , DP83869HM
When the appropriate WoL pattern has been properly received by the PHY, there is configurability for the trigger generated by the PHY. System designs have the option to have the trigger be a pulse waveform as long as 8, 16, 32, or 64 cycles of a 125MHz clock, or be a latch-able level change which can cause the PHY to generate a high signal. The signal's latch can only be cleared by writing to a field to clear.
In Figure 2-2, the PHY is set to output a pulse with 256.3ns long. This is equivalent to 32 periods of a 125MHz waveform.
In Figure 2-3, the PHY is set to output a pulse with 512.4ns long. This is equivalent to 64 periods of a 125MHz waveform.
In Figure 2-4, the PHY is set to a level change upon receipt of the appropriate frame. This level change is active high and can only be cleared with a register write to the WoL configuration register.