SNLA438 September   2023 DP83822H , DP83822HF , DP83822I , DP83822IF , DP83826E , DP83826I , DP83867CS , DP83867E , DP83867IS , DP83869HM

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2PROFINET Specification Requirements
  6. 3Ethernet PHY Setup
    1. 3.1 DP83822
      1. 3.1.1 DP83822 Hardware Bootstrap Configurations
      2. 3.1.2 DP83822 Register Configuration
    2. 3.2 DP83826
      1. 3.2.1 DP83826 Hardware Bootstrap Configuration
      2. 3.2.2 DP83826 Register Configuration
    3. 3.3 DP83867
      1. 3.3.1 DP83867 Hardware Bootstrap Configurations
      2. 3.3.2 DP83867 Register Configuration
    4. 3.4 DP83869
      1. 3.4.1 DP83869 Hardware Bootstrap Configurations
      2. 3.4.2 DP83869 Register Configuration
  7. 4Summary
  8. 5References

3.2.1 DP83826 Hardware Bootstrap Configuration

DP83826 uses many of the functional pins as strap options to place the device into specific modes of operation. The values of these pins are sampled at power up or hard reset. During software resets, the strap options are internally reloaded from the values sampled at power up or hard reset.

GUID-C6CEBA76-B077-461C-83AB-6E8D3B47A14F-low.gif Figure 3-4 Strap Circuit
Table 3-4 DP83826 100Base-TX
DP83826 100Base-TX Strapping Pin RH(kΩ) RL(kΩ) Remarks

Enhanced Mode,

MAC Inteface: MII,

10/100 Full Duplex,

Auto-Negotiation Enabled,

Auto-MDIX Enabled,

FLD Enabled,

 Mode Select 2.49 Open Enhanced Mode
RX_D0 Open Open Auto-negotiation Enabled
RX_D1 Open Open Auto MDI-X Enable
RX_D2 Open Open MII
RX_D3 2.49 Open FLD Enable