SNOU176B October   2020  – March 2022

PRODUCTION DATA  

  1.   Trademarks
  2. 1 General TI High Voltage Evaluation User Safety Guidelines
    1. 1.1 Safety and Precautions
  3. 2 Introduction
    1. 2.1 LMG342XEVM-04X Daughter Card
      1. 2.1.1 FAULT and OC
      2. 2.1.2 Power Pins
      3. 2.1.3 Bootstrap Mode
      4. 2.1.4 Heat Sink
    2. 2.2 Mother Boards
      1. 2.2.1 Bias Supply
      2. 2.2.2 PWM Input
      3. 2.2.3 Fault Protection
    3. 2.3 Typical Applications
    4. 2.4 Features
  4. 3  LMG342XEVM-04X Schematic
  5. 4 Mother Board Schematic
  6. 5 Recommended Footprint
  7. 6 Test Equipment
  8. 7 Test Procedure When Paired With LMG342X-BB-EVM
    1. 7.1 Setup
    2. 7.2 Start-Up and Operating Procedure
    3. 7.3 Test Results
    4. 7.4 Shutdown Procedure
    5. 7.5 Additional Operating Notes
  9. 8 Test Procedure When Paired With LMG34XX-BB-EVM
    1. 8.1 Setup
      1. 8.1.1 List of Test Points
      2. 8.1.2 List of Terminals
    2. 8.2 Start-Up and Operating Procedure
    3. 8.3 Shutdown Procedure
    4. 8.4 Additional Operation Notes
  10. 9 Bill of Materials
  11. 10Revision History

2.2.3 Fault Protection

There is an option to disable the PWM input to the daughter card in the event of a fault signal from the LMG342XEVM-04X. When the FAULT Protect jumper is placed in the EN mode, PWM is disabled when either LMG342XR0X0 has an active fault. This disable is not latching, so PWM immediately resumes when the fault clears. If the FAULT Protect mode is not desired, that mode can be disabled by placing the jumper in the DIS position. The FAULT LED will still illuminate when either LMG342XR0X0 has an active fault, regardless of the position of FAULT Protect jumper.