SNVU865 june   2023 LP87702-Q1

 

  1.   1
  2.   LP877020-Q1 Technical Reference Manual
  3.   Trademarks
  4. 1Introduction
  5. 2Register Bits Loaded From OTP Memory
  6. 3Revision History

1 Introduction

This Technical Reference Manual can be used as a reference for the LP8770-Q1 default register bits after OTP memory download. This Technical Reference Manual does not provide information about the electrical characteristics, external components, package, or the functionality of the device. For this information and the full register map, refer to the LP87702-Q1 Dual Buck Converter and 5-V Boost With Diagnostic Functions data sheet and LP877020-Q1 Configuration Guide.

Main OTP settings for power rails are listed in Table 1-1. Full list of register bits loaded from OTP memory is shown in Section 2.

Table 1-1 Main OTP Settings for Power Rails
DESCRIPTIONBIT NAMELP877021
Device IdentificationOTP configurationOTP_ID38
Revision for OTP_IDOTP_REV1
BUCK0Output voltageBUCK0_VSET1.8V
Enable, EN-pin or I2C registerBUCK0_EN_PIN_CTRL, BUCK0_ENEN1
Force PWMBUCK0_FPWMYes
Peak current limitBUCK0_ILIM4 A
Maximum load currentN/A3 A
BUCK1Output voltageBUCK1_VSET1.1V
Enable, EN-pin or I2C registerBUCK1_EN_PIN_CTRL, BUCK1_ENEN1
Force PWMBUCK1_FPWMYes
Peak current limitBUCK1_ILIM4.5 A
Maximum load currentN/A3.5 A
BOOSTMode, boost or bypassMode control bit is not in customer register spaceBoost
Output voltageBOOST_VSET5 V
Enable, EN-pin or I2C registerBOOST_EN_PIN_CTRL, BOOST_ENNRST
Peak current limitBOOST_ILIM0, BOOST_ILIM11.4A
Maximum load currentN/A0.6 A
VANAVANA over-voltage thresholdVANA_OVP_SEL (selection bit is not in customer register space)4.3V rising

There are a few important connections to ensure the LP877021-Q1 is configured correctly. Good example of how to connect the LP877021-Q1 PMIC is shown in Figure 1-1 .

GUID-20230618-SS0I-RJXF-BRK7-WSLPH4KMJW3B-low.svg Figure 1-1 Typical Connection to LP877021-Q1