SPRACY9 March   2023 TMS320F2800132 , TMS320F2800132 , TMS320F2800133 , TMS320F2800133 , TMS320F2800135 , TMS320F2800135 , TMS320F2800137 , TMS320F2800137 , TMS320F2800152-Q1 , TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157 , TMS320F2800157-Q1 , TMS320F2800157-Q1 , TMS320F280021 , TMS320F280021 , TMS320F280021-Q1 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280023C , TMS320F280025 , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280033 , TMS320F280034 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C , TMS320F280049C-Q1 , TMS320F280049C-Q1 , TMS320F28075 , TMS320F28075 , TMS320F28075-Q1 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28076 , TMS320F28374D , TMS320F28374D , TMS320F28374S , TMS320F28374S , TMS320F28375D , TMS320F28375D , TMS320F28375S , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376D , TMS320F28376S , TMS320F28376S , TMS320F28377D , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378D , TMS320F28378S , TMS320F28378S , TMS320F28379D , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28379S , TMS320F28384D , TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388D , TMS320F28388S , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1 , TMS320F28P659SH-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Mechanism of ADC Input Settling
    2. 1.2 Symptoms of Inadequate Settling
      1. 1.2.1 Distortion
      2. 1.2.2 Memory Cross-Talk
      3. 1.2.3 Accuracy
      4. 1.2.4 C2000 ADC Architecture
    3. 1.3 Resources
      1. 1.3.1 TINA-TI SPICE-Based Analog Simulation Program
      2. 1.3.2 PSPICE for TI Design and Simulation Tool
      3. 1.3.3 TI Precision Labs - SAR ADC Input Driver Design Series
      4. 1.3.4 Analog Engineer's Calculator
      5. 1.3.5 Related Application Reports
      6. 1.3.6 PSpice for TI ADC Input Models
  4. 2Input Settling Design Steps
    1. 2.1 Select the ADC
    2. 2.2 Find the Minimum Op-Amp Bandwidth and RC Filter Ranges
      1. 2.2.1 Select Type
      2. 2.2.2 Resolution
      3. 2.2.3 Csh
      4. 2.2.4 Full-Scale Range
      5. 2.2.5 Acquisition Time
      6. 2.2.6 Outputs
      7. 2.2.7 Math Behind the Calculator
    3. 2.3 Select an Op-Amp
    4. 2.4 Verify the Op-Amp Model
    5. 2.5 Build the ADC Input Model
      1. 2.5.1 Vin
      2. 2.5.2 Voa, Voa_SS, and Verror
      3. 2.5.3 Rs, Cs, and Vcont
      4. 2.5.4 Ch, Ron, and Cp
      5. 2.5.5 S+H Switch, Discharge Switch, tacq, and tdis
    6. 2.6 Refine RC Filter Values Via Simulation
    7. 2.7 Perform Final Simulations
    8. 2.8 Input Design Worksheet
  5. 3Example Circuit Design
    1. 3.1  Select the ADC
    2. 3.2  Find the Minimum Op-Amp Bandwidth and RC Filter Ranges
    3. 3.3  Verify the Op-Amp Model
    4. 3.4  Build the ADC Input Model
    5. 3.5  Bias Point Analysis to Determine Voa_ss
    6. 3.6  Transient Analysis to Determine Voa_ss
    7. 3.7  Perform Initial Transient Analysis
    8. 3.8  Iterative Approach to Refine RC Filter Values
    9. 3.9  Perform Final Transient Analysis
    10. 3.10 Perform Final Transient Analysis
    11. 3.11 Further Refinement
    12. 3.12 Further Simulations
    13. 3.13 Completed Worksheet
  6. 4Working With Existing Circuits or Additional Constraints
    1. 4.1 Existing Circuits
      1. 4.1.1 Brief Overview of Charge Sharing
      2. 4.1.2 Charge Sharing Example
      3. 4.1.3 Additional Resources for Charge Sharing
    2. 4.2 Pre-Selected Op-Amp
      1. 4.2.1 Pre-Selected Op-Amp Example
    3. 4.3 Pre-Selected Rs and Cs Values
      1. 4.3.1 Analytical Solution for ADC Acquisition Time
      2. 4.3.2 Example Analytical Solution for ADC Acquisition Time
  7. 5Summary
  8. 6References

4.1.2 Charge Sharing Example

In the example circuit in Figure 4-1, Cs has been set to approximately 2(N+1) x Ch and the sample trigger rate is set to 100 kHz.

GUID-8D8ED428-E651-4A14-9A09-4DE8532DF5B0-low.jpg Figure 4-1 Example Circuit Utilizing Charge Sharing

Figure 4-2 shows the pin transient over many sampling cycles when Rs is 100 Ω. It can be seen that the voltage on the pin (which is the voltage directly on Cs) recovers to within 1/2 LSBs in the time between conversions. This will result in good ADC input settling using a very short S+H window as long as the sample-rate remains at or below 100 ksps.

GUID-8011620C-1635-483D-BEE5-583EC028C97E-low.jpg Figure 4-2 Cs Voltage With Rs = 100 Ω

Now consider the results in Figure 4-3. Rs has been set to 1k Ω. In this case, the voltage on Cs is slowly depleted sample-by-sample until an equilibrium is reached. At equilibrium, the pin voltage has an error of about 3.5 mV. Even though Ch will quickly match the Cs voltage during the S+H phase, the voltage on Cs has a significant error.

GUID-7A72C638-C4BC-4F2D-9B09-DFF1F00E275D-low.jpg Figure 4-3 Cs Voltage With Rs = 1k Ω

To resolve this error, either Rs would need to be decreased or the sample rate would have to be reduced.

This example underscores the importance of simulating circuits with large Cs or Rs over many cycles.