SPRAD21E May 2023 – February 2024 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62P , AM62P-Q1
Many of the processor IOs support multiplexing of functions. The IO function can be chosen from multiple functions. The list of functions available for each pad is enumerated in SIGNAL NAME column in the Pin Attributes table of the device-specific data sheet.
The desired function is selected via the MUXMODE field of the associated pad configuration register. The PADCFG_CTRL0_CFG0_PADCONFIG0 to PADCFG_CTRL0_CFG0_PADCONFIG150 registers control the signal multiplexing of IOs in the processor Main Domain and MCU_PADCFG_CTRL0_CFG0_PADCONFIG0 to MCU_PADCFG_CTRL0_CFG0_PADCONFIG33 registers control the signal multiplexing of IOs in the processor MCU Domain.
The Pad Configuration Ball Names table in the Pad Configuration Registers section of the device-specific TRM summarizes the Bit Field Reset Values for all the PADCONFIG registers. Follow the notes listed at the end of the table while configuring the PADCONFIG registers. The RXACTIVE bit must never be set without a valid logic state being sourced to the pin associated with the respective PADCONFIG register. This is important since a floating input could damage the processor or affect reliability.