SPRADD9 September   2023 TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137 , TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1 , TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Optimized ePWM Configurations
    1. 1.1 Cycle by Cycle (CBC) Protection
    2. 1.2 Reverse Current Control
    3. 1.3 ePWM Configurations Proposed
  5. 2How to Better Use the CMPSS for Totem Pole PFC
  6. 3How to Control the Slow Frequency MOSFETs
  7. 4How to Implement Reliable Zero-Crossing Detection
  8. 5How to Implement 2 Phase Interleaved Control
  9. 6References

How to Better Use the CMPSS for Totem Pole PFC

As discussed in Section 1, it is required to detect both the reverse current and the overcurrent events for totem pole PFC, so CMPSS can be used to save the external comparator circuits. In order to use the minimum CMPSS amount, the diagram in Figure 2-1 shows how to use one CMPSS for single phase totem pole PFC. The inductor current is routed to both high side comparator CMPSS1_H and low side comparator CMPSS1_L, while CMPSS1_H is for overcurrent detection, and CMPSS_L for reverse current detection.

GUID-20230825-SS0I-QTTG-FRDK-QVS2VSWZ1XR8-low.svg Figure 2-1 CMPSS Configurations

As for overcurrent protection for both positive cycle and negative cycle, it is required to change the DAC value with different thresholds at the zero-crossing point. In addition, to select one of DCxEVT1/2 events as the T1 source, specific high or low level effective should be defined for the CMPSS1_H output. During the positive cycle, when the overcurrent event occurs, the output of CMPSS1_H is high level effective, while in the negative cycle, the output of CMPSS1_H is low level effective. To address this, the CMPSS1_H output could be inverted with the COMPCTL[COMPHINV] register in the negative cycle so as to keep the same high level effective logic for the protection scheme regardless of the VAC polarity.

As for the reverse current detection, note that the reverse current is always in the opposite polarity of the VAC waveform, which is the negative current spike at the positive cycle, and the positive current spike at the negative cycle. Therefore, similar with the CMPSS1_H configurations, it is also required to change the DAC value and invert the output polarity in the negative cycle for CMPSS1_L.

For totem pole PFC, during the zero-crossing point, there exists a dead time when all the PWM signals shut down, so it is safe and also suggested to change the DAC value and output polarity of CMPSS during that time. According to the device-specific data sheet, the CMPSS DAC settling time is within 1 µs, which is fast enough to handle any change.

GUID-20230825-SS0I-PTRS-TRVD-KHDFLSR5JG2M-low.svg Figure 2-2 CMPSS Module Block Diagram