SPRADG5 January   2024 DRA821U , DRA821U-Q1 , TDA4AL-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VM , TDA4VM-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1UART Introduction
    1. 1.1 Jacinto 7 UART Overview
    2. 1.2 Jacinto 7 UART Features
    3. 1.3 Jacinto 7 UART Functional Introduction
  5. 2UART Usage Overview
    1. 2.1 WKUP_UART0 Usage
    2. 2.2 MCU_UART0 Usage
    3. 2.3 MAIN_UARTx Usage
  6. 3Log Level Design on Software Module
  7. 4Change UART Instance
    1. 4.1 Change MAIN_UARTx for MAIN Domain
    2. 4.2 Set Standalone UART Port for DSP/MCU
  8. 5Summary
  9. 6References

1.2 Jacinto 7 UART Features

Jacinto 7 UART includes the following features:

  • 16C750-compatible
  • RS-485 external transceiver auto flow control support
  • 64-byte FIFO buffer for receiver and 64-byte FIFO buffer for transmitter
  • Programmable interrupt trigger levels for FIFOs
  • Programmable sleep mode
  • The 48 MHz functional clock is default option and allows baud rates up to 3.6 Mbps
  • Auto-baud between 1200 bits/s and 115.2 Kbits/s (only when 48 MHz function clock is used)
  • Optional multi-drop transmission
  • Configurable time-guard feature
  • Configurable data format:
    • Data bit: 5, 6, 7, 8, or 9 bits
    • Parity bit: Even, odd, none
    • Stop-bit: 1, 1.5, 2 bit(s)
  • Flow control: Hardware (RTS/CTS) or software (XON/XOFF)
  • False start bit detection
  • Line break generation and detection
  • Fully prioritized interrupt system controls
  • Internal test and loopback capabilities
  • Modem control functions (CTS, RTS)
  • Module instance has extended modem control signals (DCD, RI, DTR, DSR)