SPRUIU9B August   2020  – September 2022 TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28P550SJ , TMS320F28P559SJ-Q1

 

  1.   Live Firmware Update Without Device Reset on C2000 MCUs
  2.   Trademarks
  3. 1Introduction
  4. 2Key Innovations
  5. 3Building Blocks for LFU
  6. 4Details of Proposed Solution
    1. 4.1 Flash Bank Organization
    2. 4.2 LFU Concepts and Factors Impacting Performance
    3. 4.3 Hardware Support for LFU
      1. 4.3.1 Multiple Flash Banks
      2. 4.3.2 Interrupt Vector Table Swap
      3. 4.3.3 RAM Block Swap
      4. 4.3.4 Hardware Register Flags
    4. 4.4 LFU Compiler Support
    5. 4.5 Application LFU Flow
  7. 5Results and Conclusion
  8. 6Revision History

Interrupt Vector Table Swap

Multiple components of switchover time were analyzed to assess optimization opportunities and the update of the interrupt vector map entries was found to be one of the prime factors impacting switchover time. The number of vectors to be updated varies from a few to the entire table (192 vectors). The update for a single entry can take about 5 cycles and hence the update of the vector table itself can take up to 960 cycles (4.8 us at 200MHz).

In order to reduce the switchover time, a shadow vector memory and capability to swap it with active vector memory is implemented. The switchover code can update the shadow vector memory when the application execution is in progress. Once the vector memory is updated, the swap be completed in one clock cycle. Both memories can be used in ping-pong fashion for successive software upgrades.

A representative implementation of Interrupt vector swap is shown in Figure 4-2. Figure 4-2(a) is the configuration before swap and Figure 4-2(b) after the swap. The overall vector memory is divided into two blocks – Block A that spans from address 0x0000_0D00 to 0x0000_0EFF and Block B that spans from address 0x0100_0900 to 0x0100_0AFF. Block A holds the active vector table and Block B holds the shadow vector table. During LFU, shadow memory entries get updated before switchover, and the swap is executed during switchover. This reduces the switchover time from a maximum of 960 cycles to a single cycle.

Figure 4-2 Interrupt Vector Swap