SBAU435 February   2024 ADS127L18

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1  EVM Analog Input Options
    2. 2.2  Power Requirements
    3. 2.3  ADC Connections and Decoupling
    4. 2.4  ADC Input Amplifiers
    5. 2.5  VCOM Buffer
    6. 2.6  Voltage Reference
    7. 2.7  Reference Buffer
    8. 2.8  Clock Tree
    9. 2.9  Serial Interface
    10. 2.10 EEPROM
    11. 2.11 Power Supplies
    12. 2.12 Low Dropout Regulator (LDO)
  9. 3Software
    1. 3.1 Software Description
    2. 3.2 ADS127L18 EVM Software Installation
  10. 4Implementation Results
    1. 4.1 EVM Operation
      1. 4.1.1 Evaluation Setup
      2. 4.1.2 Optional EVM Connections
      3. 4.1.3 EVM Register Settings
      4. 4.1.4 ADC Capture Settings
        1. 4.1.4.1 ADC Configuration
        2. 4.1.4.2 Clocking Configuration
        3. 4.1.4.3 SPI and Data Port Configuration
        4. 4.1.4.4 Filter Configuration
        5. 4.1.4.5 Channel Configuration
      5. 4.1.5 Time Domain Display
      6. 4.1.6 Spectral Analysis Display
      7. 4.1.7 Histogram Analysis Display
  11. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  12. 6Additional Information
    1. 6.1 Trademarks
  13. 7Related Documentation
    1. 7.1 Supplemental Content

1.3 Specification

The following specifications are applicable to the ADS127L18EVM board and the PHI board.

Table 1-1 ADS127L18EVM-PDK Specifications
PARAMETERCONDITIONSVALUE
TemperatureRecommended operating free-air temperature range, TA15°C ≤ TA ≤ 35°C
Power supply input range (unipolar)

Recommended voltage input range for J6 or J7 (+Vin) verses GND

5.5V ≤ +Vin ≤ 6.5V

Supply current range |Is|

0.25A ≤ |Is| ≤ 0.5A

Power supply input range (bipolar)

Recommended voltage

input range for J7 (-Vin) verses GND

-6.5V ≤ -Vin ≤ -5.5V

Supply current range |Is|

0.25A ≤ |Is| ≤ 0.5A

Input voltage range

Absolute input voltage verses GND for ChxP and ChxN SMA inputs

-5V ≤ Chx ≤ 5V

VCOM output

Maximum fault voltage verses GND (external source fault applied to SMA J8)

0V ≤ VCOM ≤ 2.6V

VCOM output voltage verses GND (SMA J8)

2.4V ≤ VCOM ≤ 2.6V

EXT clock

Recommended voltage range (VCLK) verses GND

Logic Level High (VCLKh)

1.2V ≤ VCLKh ≤ 1.9V

Logic Level Low (VCLKl)0V ≤ VCLKl ≤ 0.5V

Recommended frequency range (fCLK)

0.5MHz ≤ fCLK ≤ 33.6MHz

External digital IO

External logic levels connected to headers J3, J4, J5 verses GND

Logic Level High (VIOh)

1.2V ≤ VIOh ≤ 1.9V

Logic Level Low (VIOl)

0V ≤ VIOl ≤ 0.5V

ADS127L18 AVDD1 to AVSS

Recommended voltage range (R5 removed), external source

Max-speed mode

4.5V ≤ AVDD1 ≤ 5.5V

High-speed mode

4.5V ≤ AVDD1 ≤ 5.5V

Mid-speed mode

3V ≤ AVDD1 ≤ 5.5V

Low-speed mode

2.85V ≤ AVDD1 ≤ 5.5V

ADS127L18 AVDD1 to GND

Recommended voltage range (R5 removed), external source, DGND = GND

1.65V ≤ AVDD1

ADS127L18 |AVSS/AVDD1| ratio to GND

Recommended absolute ratio range, external source,

DGND = GND

|AVSS/AVDD1| ≤ 1.2V/V

ADS127L18 AVDD2 to AVSS

Recommended voltage range (R6 removed), external source1.74V ≤ AVDD2 ≤ 5.5V

ADS127L18 AVSS to GND

Recommended voltage range (JP2 2-3 position), DGND = GND

-2.75V ≤ AVSS ≤ 0V

ADS127L18 IOVDD to GND

Recommended voltage range (R7 removed), external source, DGND = GND

1.65V ≤ IOVDD ≤ 1.95V

ADS127L18 Reference REFP to AVSS

Recommended voltage range (R62, R63, R75 removed), external source

Low ref range

0.5V ≤ REFP ≤ 2.75V

High ref range

1V ≤ REFP ≤ AVDD1