SCEA143 December 2023 SN74AVC8T245 , SN74AVC8T245-Q1 , SN74AXC8T245 , SN74AXC8T245-Q1 , TXV0106 , TXV0106-Q1 , TXV0108 , TXV0108-Q1
Parameter | TXV0108 (ns) | Competitor (ps) | TXV RGMII Margin | Comp RGMII Margin |
---|---|---|---|---|
10 pF Skewrf / Skewfr | 164 / 61 | 39 / 257 | 67 % better than spec | 49 % better than spec |
10 pF Rise/Fall Time | 698/ 534 | 900 / 833 | 10 % better than spec | 20 % worst than spec |
15 pF Skewrf / Skewfr | 53 / 181 | 195 / 93 | 64 % better than spec | 61 % better than spec |
15 pF Rise/Fall Time | 752 / 652 | 1200 / 1300 | 0.3 % worst than spec | 73 % worst than spec |
As mentioned, skew between MAC and PHY can lead to data errors and performance issues. Today, complex systems tend to use connectors or longer traces in designing printed circuit boards (PCB), incorporating additional parasitic capacitance. Choosing the correct level-shifter for buffering, can increase the chances of overcoming such design challenges between the hosts or peripherals.
RGMII standard assumes 5 pF loading conditions for the interface's I/O, and can increase as design complexities increases with additional parasitic capacitance. Designers can use TXV for buffering more than the assumed standard load condition to support RGMII’s timing conditions for data and clock signals.