4 Pin Failure Mode Analysis (Pin FMA)

Potential spordaic behavior where device may respond and operate correctly or not work at all, may cause system level issues depending on what the GPIOs are tied to.

If P03 and P04 are OUTPUTs but logic levels are not the same (one is OUTPUT LOW and other is OUTPUT HIGH), then contention between the two will occur. If IoH exceeds 10mA then damage may occur but may not be instantaneous. Failures over time may occur.

If P03 and P04 are OUTPUTs and logic levels are the same (both are OUTPUT HIGH or OUTPUT LOW), no damage is expected but some leakage current may occur.

If P03 and P04 are both INPUTs, no damage is expected if both have the same pull-up or pull-down configuration. If opposite pull-up and pull-down configuration exists, excess current through the input buffers could take place leading to indeterminant IO state and false interrupts.

If P03 and P04 are configured such that the pair is an OUTPUT and an INPUT, then no damage is expected.

If P04 and P05 are OUTPUTs but logic levels are not the same (one is OUTPUT LOW and other is OUTPUT HIGH), then contention between the two will occur. If IoH exceeds 10mA then damage may occur but may not be instantaneous. Failures over time may occur.

If P04 and P05 are OUTPUTs and logic levels are the same (both are OUTPUT HIGH or OUTPUT LOW), no damage is expected but some leakage current may occur.

If P04 and P05 are both INPUTs, no damage is expected if both have the same pull-up or pull-down configuration. If opposite pull-up and pull-down configuration exists, excess current through the input buffers could take place leading to indeterminant IO state and false interrupts.

If P04 and P05 are configured such that the pair is an OUTPUT and an INPUT, then no damage is expected.

If P06 and P07 are OUTPUTs but logic levels are not the same (one is OUTPUT LOW and other is OUTPUT HIGH), then contention between the two will occur. If IoH exceeds 10mA then damage may occur but may not be instantaneous. Failures over time may occur.

If P06 and P07 are OUTPUTs and logic levels are the same (both are OUTPUT HIGH or OUTPUT LOW), no damage is expected but some leakage current may occur.

If P06 and P07 are both INPUTs, no damage is expected if both have the same pull-up or pull-down configuration. If opposite pull-up and pull-down configuration exists, excess current through the input buffers could take place leading to indeterminant IO state and false interrupts.

If P06 and P07 are configured such that the pair is an OUTPUT and an INPUT, then no damage is expected.

If P07 is set to an OUTPUT LOW, no functionality or damage is expected.

If P07 is an INPUT, no damage is expect, but functionality is lost as P07 will likely not see a logic HIGH and set the INT.

If P07 is an OUTPUT HIGH, damage is likely to occur as a large IoH current flows from the pin and likely exceed the VoH limit.

If P10 is set to an OUTPUT LOW, no functionality or damage is expected.

If P10 is an INPUT, no damage is expect, but functionality is lost as P10 will likely not see a logic HIGH and set the INT.

If P10 is an OUTPUT HIGH, damage is likely to occur as a large IoH current flows from the pin and likely exceed the VoH limit.

If P10 and P11 are OUTPUTs but logic levels are not the same (one is OUTPUT LOW and other is OUTPUT HIGH), then contention between the two will occur. If IoH exceeds 10mA then damage may occur but may not be instantaneous. Failures over time may occur.

If P10 and P11 are OUTPUTs and logic levels are the same (both are OUTPUT HIGH or OUTPUT LOW), no damage is expected but some leakage current may occur.

If P10 and P11 are both INPUTs, no damage is expected if both have the same pull-up or pull-down configuration. If opposite pull-up and pull-down configuration exists, excess current through the input buffers could take place leading to indeterminant IO state and false interrupts.

If P10 and P11 are configured such that the pair is an OUTPUT and an INPUT, then no damage is expected.

If P11 and P12 are OUTPUTs but logic levels are not the same (one is OUTPUT LOW and other is OUTPUT HIGH), then contention between the two will occur. If IoH exceeds 10mA then damage may occur but may not be instantaneous. Failures over time may occur.

If P11 and P12 are OUTPUTs and logic levels are the same (both are OUTPUT HIGH or OUTPUT LOW), no damage is expected but some leakage current may occur.

If P11 and P12 are both INPUTs, no damage is expected if both have the same pull-up or pull-down configuration. If opposite pull-up and pull-down configuration exists, excess current through the input buffers could take place leading to indeterminant IO state and false interrupts.

If P11 and P12 are configured such that the pair is an OUTPUT and an INPUT, then no damage is expected.

If P13 and P14 are OUTPUTs but logic levels are not the same (one is OUTPUT LOW and other is OUTPUT HIGH), then contention between the two will occur. If IoH exceeds 10mA then damage may occur but may not be instantaneous. Failures over time may occur.

If P13 and P14 are OUTPUTs and logic levels are the same (both are OUTPUT HIGH or OUTPUT LOW), no damage is expected but some leakage current may occur.

If P13 and P14 are both INPUTs, no damage is expected if both have the same pull-up or pull-down configuration. If opposite pull-up and pull-down configuration exists, excess current through the input buffers could take place leading to indeterminant IO state and false interrupts.

If P13 and P14 are configured such that the pair is an OUTPUT and an INPUT, then no damage is expected.

If P14 and P15 are OUTPUTs but logic levels are not the same (one is OUTPUT LOW and other is OUTPUT HIGH), then contention between the two will occur. If IoH exceeds 10mA then damage may occur but may not be instantaneous. Failures over time may occur.

If P14 and P15 are OUTPUTs and logic levels are the same (both are OUTPUT HIGH or OUTPUT LOW), no damage is expected but some leakage current may occur.

If P14 and P15 are both INPUTs, no damage is expected if both have the same pull-up or pull-down configuration. If opposite pull-up and pull-down configuration exists, excess current through the input buffers could take place leading to indeterminant IO state and false interrupts.

If P14 and P15 are configured such that the pair is an OUTPUT and an INPUT, then no damage is expected.

If P15 and P16 are OUTPUTs but logic levels are not the same (one is OUTPUT LOW and other is OUTPUT HIGH), then contention between the two will occur. If IoH exceeds 10mA then damage may occur but may not be instantaneous. Failures over time may occur.

If P15 and P16 are OUTPUTs and logic levels are the same (both are OUTPUT HIGH or OUTPUT LOW), no damage is expected but some leakage current may occur.

If P15 and P16 are both INPUTs, no damage is expected if both have the same pull-up or pull-down configuration. If opposite pull-up and pull-down configuration exists, excess current through the input buffers could take place leading to indeterminant IO state and false interrupts.

If P15 and P16 are configured such that the pair is an OUTPUT and an INPUT, then no damage is expected.

If P16 and P17 are OUTPUTs but logic levels are not the same (one is OUTPUT LOW and other is OUTPUT HIGH), then contention between the two will occur. If IoH exceeds 10mA then damage may occur but may not be instantaneous. Failures over time may occur.

If P16 and P17 are OUTPUTs and logic levels are the same (both are OUTPUT HIGH or OUTPUT LOW), no damage is expected but some leakage current may occur.

If P16 and P17 are both INPUTs, no damage is expected if both have the same pull-up or pull-down configuration. If opposite pull-up and pull-down configuration exists, excess current through the input buffers could take place leading to indeterminant IO state and false interrupts.

If P16 and P17 are configured such that the pair is an OUTPUT and an INPUT, then no damage is expected.

If P17 is an INPUT, no expected damage. Functionality may be lost depending on what is connected to P17 in the system which is now also connected to A0.

If P17 is an OUTPUT HIGH and A0 is referenced to a pull up to Vcc or if P17 is an OUTPUT LOW and A0 is referenced to a logic low, then no functionality or damage is expected.

If P17 is an OUTPUT HIGH and A0 is referenced to a low through a resistor or P17 is an OUTPUT LOW and A0 is referenced to a logic HIGH through a resistor, then A0 will now be a different state than intended/designed for.

The processor will not be able to access the intended I2C target. If another I2C target shares the same address as this device, then signal integrity issues may be a concern. Device may end up being programmed incorrectly/unintentionally in this case. Functionality may be lost due to this. Direct damage is not expected though depending on how the system implements the GPIOs, damage may be possible due to unintended programming.

I2C communication will be lost both to the device and to the system's I2C bus.

Functionality is lost, but no damage expected.

Device is likely to be damaged during ACKs and read transaction due to large excessive current through pin. If IoL exceeds 6 mA at 85°C or less, device may be damaged. Damage may not be instanteous but may occur over time.

VoL from device may also be too large for master to accept as a valid low during ACKs.

If INT is de-asserted/HIGH then there should not be concerns outside of potential leakage currents.

When INT asserts, large IoL current flows from VCC to GND through the INT pin, if VCC of device is low then the NFET (of INT) saturates and VoL on INT clamps as well as the IoL current. Damage may occur, but may not break the device instantly, likely damage over time.

From a system level, processor looking at the INT may not see an interrupt as the VoL could be larger than the ViL of a processor.

Device address may change if A1 is tied to a pull-up resistor whenever INT asserts. Address would change back when INT de-asserts.

If A1 is tied to a pull-down resistor, voltage at A1 may be at a mid voltage due to resistor divider between A1's pull down and INT's pull-up. Address of device may change due to any noise/coupling onto the pin. Increased leakage current on supply would be seen. When INT asserts, the address will set back to low. INT may also never go above ViH for any processor/mcu looking at the INT line. Additional leakage current may be expected at the processor/mcu input for the INT.

Functionality may be lost.

If A1 is tied to a pull-down resistor, A1 and RESET will form a voltage divider and the voltage at these pins will settle somewhere mid rail if pull-up and pull-down resistors are equal in value. RESET and device address may be in an unknown state because they are not above/below ViH/ViL levels. Noise coupling onto these pins may toggle reset. Assume functionality is lost.

If A1 is tied HIGH and we assume RESET is tied HIGH with pull-up resistors, no errors are expected.

If P02 is set to an OUTPUT HIGH, then there should be no concerns outside of leakage currents.

If P02 is set to an OUTPUT LOW, then large current from VCC to GND through the pin is expected. If current exceeds 25mA at 85C or lower then the device may be damaged.

If P02 is set to an INPUT, then there should be no concerns outside of leakage currents. Note functionality of the input will be lost because P00 will be held HIGH and will not ever go low.

If P03 is set to an OUTPUT HIGH, then there should be no concerns outside of leakage currents.

If P03 is set to an OUTPUT LOW, then large current from VCC to GND through the pin is expected. If current exceeds 25mA at 85C or lower then the device may be damaged.

If P03 is set to an INPUT, then there should be no concerns outside of leakage currents. Note functionality of the input will be lost because P00 will be held HIGH and will not ever go low.

If P04 is set to an OUTPUT HIGH, then there should be no concerns outside of leakage currents.

If P04 is set to an OUTPUT LOW, then large current from VCC to GND through the pin is expected. If current exceeds 25mA at 85C or lower then the device may be damaged.

If P04 is set to an INPUT, then there should be no concerns outside of leakage currents. Note functionality of the input will be lost because P00 will be held HIGH and will not ever go low.

If P05 is set to an OUTPUT HIGH, then there should be no concerns outside of leakage currents.

If P05 is set to an OUTPUT LOW, then large current from VCC to GND through the pin is expected. If current exceeds 25mA at 85C or lower then the device may be damaged.

If P05 is set to an INPUT, then there should be no concerns outside of leakage currents. Note functionality of the input will be lost because P00 will be held HIGH and will not ever go low.

If P06 is set to an OUTPUT HIGH, then there should be no concerns outside of leakage currents.

If P06 is set to an OUTPUT LOW, then large current from VCC to GND through the pin is expected. If current exceeds 25mA at 85C or lower then the device may be damaged.

If P06 is set to an INPUT, then there should be no concerns outside of leakage currents. Note functionality of the input will be lost because P00 will be held HIGH and will not ever go low.

If P07 is set to an OUTPUT HIGH, then there should be no concerns outside of leakage currents.

If P07 is set to an OUTPUT LOW, then large current from VCC to GND through the pin is expected. If current exceeds 25mA at 85C or lower then the device may be damaged.

If P07 is set to an INPUT, then there should be no concerns outside of leakage currents. Note functionality of the input will be lost because P00 will be held HIGH and will not ever go low.

Device may be damaged due to biasing of internal substrates which were previously only supposed to be biased to GND.

If P10 is set to an OUTPUT HIGH, then there should be no concerns outside of leakage currents.

If P10 is set to an OUTPUT LOW, then large current from VCC to GND through the pin is expected. If current exceeds 25mA at 85C or lower then the device may be damaged.

If P10 is set to an INPUT, then there should be no concerns outside of leakage currents. Note functionality of the input will be lost because P00 will be held HIGH and will not ever go low.

If P11 is set to an OUTPUT HIGH, then there should be no concerns outside of leakage currents.

If P11 is set to an OUTPUT LOW, then large current from VCC to GND through the pin is expected. If current exceeds 25mA at 85C or lower then the device may be damaged.

If P11 is set to an INPUT, then there should be no concerns outside of leakage currents. Note functionality of the input will be lost because P00 will be held HIGH and will not ever go low.

If P12 is set to an OUTPUT HIGH, then there should be no concerns outside of leakage currents.

If P12 is set to an OUTPUT LOW, then large current from VCC to GND through the pin is expected. If current exceeds 25mA at 85C or lower then the device may be damaged.

If P12 is set to an INPUT, then there should be no concerns outside of leakage currents. Note functionality of the input will be lost because P00 will be held HIGH and will not ever go low.

If P13 is set to an OUTPUT HIGH, then there should be no concerns outside of leakage currents.

If P13 is set to an OUTPUT LOW, then large current from VCC to GND through the pin is expected. If current exceeds 25mA at 85C or lower then the device may be damaged.

If P13 is set to an INPUT, then there should be no concerns outside of leakage currents. Note functionality of the input will be lost because P00 will be held HIGH and will not ever go low.

If P14 is set to an OUTPUT HIGH, then there should be no concerns outside of leakage currents.

If P14 is set to an OUTPUT LOW, then large current from VCC to GND through the pin is expected. If current exceeds 25mA at 85C or lower then the device may be damaged.

If P14 is set to an INPUT, then there should be no concerns outside of leakage currents. Note functionality of the input will be lost because P00 will be held HIGH and will not ever go low.

If P15 is set to an OUTPUT HIGH, then there should be no concerns outside of leakage currents.

If P15 is set to an OUTPUT LOW, then large current from VCC to GND through the pin is expected. If current exceeds 25mA at 85C or lower then the device may be damaged.

If P15 is set to an INPUT, then there should be no concerns outside of leakage currents. Note functionality of the input will be lost because P00 will be held HIGH and will not ever go low.

If P16 is set to an OUTPUT HIGH, then there should be no concerns outside of leakage currents.

If P16 is set to an OUTPUT LOW, then large current from VCC to GND through the pin is expected. If current exceeds 25mA at 85C or lower then the device may be damaged.

If P16 is set to an INPUT, then there should be no concerns outside of leakage currents. Note functionality of the input will be lost because P00 will be held HIGH and will not ever go low.

If P17 is set to an OUTPUT HIGH, then there should be no concerns outside of leakage currents.

If P17 is set to an OUTPUT LOW, then large current from VCC to GND through the pin is expected. If current exceeds 25mA at 85C or lower then the device may be damaged.

If P17 is set to an INPUT, then there should be no concerns outside of leakage currents. Note functionality of the input will be lost because P00 will be held HIGH and will not ever go low.

If A0 is tied to a pull up voltage, then there should be no concerns outside of leakage currents.

If A0 is referenced to GND with a pull up resistor, then the device will now interpret A0 as a logic HIGH and the I2C Controller will not be able to communicate to the device (I2C target address has changed). If there is another device on the bus with the same address, then there could be signal integrity concerns or GPIOs could be set to the wrong settings.

Worst case is A0 is tied directly to GND. If VCC were shorted to A1 in this case, we would have a direct short to GND. No damage is expected to our device but may cause damage to power supplying rail

SCL is an input, so no damage is expected to the device. The device may not see a valid VoL though as the I2C controller will likely have a larger VoL due to the excess current. Worst case for device is lose of I2C communication due to VoL I2C controller> ViL device.

Damage to the processor may occur or any device which supports clock stretching.

Device may be damaged during ACKs and read transaction due to large excessive current through pin. Damage may not be instanteous but may occur over time.

VoL from device may also be too large for I2C Controller to accept as a valid low during ACKs.

VCC is shorted to VCC, this is expected and no damage should occur.

If INT is de-asserted/HIGH then there should not be concerns outside of potential leakage currents.

When INT asserts, large IoL current flows from VCC to GND through the INT pin, if VCC of device is low then the NFET (of INT) saturates and VoL on INT clamps as well as the IoL current. Damage may occur, but may not break the device instantly, likely damage over time.

From a system level, processor looking at the INT may not see an interrupt as the VoL could be larger than the ViL of a processor.

If A1 is tied to a pull up voltage, then there should be no concerns outside of leakage currents.

If A1 is referenced to GND with a pull up resistor, then the device interprets A1 as a logic HIGH and the master/processor is not able to communicate to the device (I2C target address has changed).

If there is another device on the bus with the same address, then there could be signal integrity concerns or GPIOs could be set to the wrong settings.

Worst case is A1 is tied directly to GND. If VCC were shorted to A1 in this case, ther is a direct short to GND. No damage is expected to our device, but may cause damage to power supplying rail

If RESET is tied to a pull up voltage, then there should be no concerns outside of leakage currents. If processor or any external circuit attempts to drive #RESET low, it may see a large current from Vcc to GND. The external driver may be damaged. Device will not be able to be reset through this hardware pin.