SLAU144K December 2004 – August 2022 MSP430AFE221 , MSP430AFE222 , MSP430AFE223 , MSP430AFE231 , MSP430AFE232 , MSP430AFE233 , MSP430AFE251 , MSP430AFE252 , MSP430AFE253 , MSP430F2001 , MSP430F2002 , MSP430F2003 , MSP430F2011 , MSP430F2012 , MSP430F2013 , MSP430F2101 , MSP430F2111 , MSP430F2112 , MSP430F2121 , MSP430F2122 , MSP430F2131 , MSP430F2132 , MSP430F2132-EP , MSP430F2232 , MSP430F2234 , MSP430F2252 , MSP430F2252-Q1 , MSP430F2254 , MSP430F2272 , MSP430F2272-Q1 , MSP430F2274 , MSP430F2274-EP , MSP430F233 , MSP430F2330 , MSP430F235 , MSP430F2350 , MSP430F2370 , MSP430F2410 , MSP430F2416 , MSP430F2417 , MSP430F2418 , MSP430F2419 , MSP430F247 , MSP430F2471 , MSP430F248 , MSP430F2481 , MSP430F249 , MSP430F2491 , MSP430F2616 , MSP430F2617 , MSP430F2618 , MSP430F2619 , MSP430G2001 , MSP430G2101 , MSP430G2102 , MSP430G2111 , MSP430G2112 , MSP430G2121 , MSP430G2131 , MSP430G2132 , MSP430G2152 , MSP430G2153 , MSP430G2201 , MSP430G2201-Q1 , MSP430G2202 , MSP430G2203 , MSP430G2210 , MSP430G2211 , MSP430G2212 , MSP430G2213 , MSP430G2221 , MSP430G2230 , MSP430G2231 , MSP430G2231-Q1 , MSP430G2232 , MSP430G2233 , MSP430G2252 , MSP430G2253 , MSP430G2302 , MSP430G2303 , MSP430G2312 , MSP430G2313 , MSP430G2332 , MSP430G2333 , MSP430G2352 , MSP430G2353 , MSP430G2402 , MSP430G2403 , MSP430G2412 , MSP430G2413 , MSP430G2432 , MSP430G2433 , MSP430G2444 , MSP430G2452 , MSP430G2453 , MSP430G2513 , MSP430G2533 , MSP430G2544 , MSP430G2553 , MSP430G2744 , MSP430G2755 , MSP430G2855 , MSP430G2955 , MSP430TCH5E
Table 26-5 lists the memory-mapped registers for the SD16_A.
Address | Acronym | Register Name | Type | Reset | Section |
---|---|---|---|---|---|
100h | SD16CTL | SD16_A control | Read/write | 00h with PUC | Section 26.4.1 |
102h | SD16CCTL0 | SD16_A channel 0 control | Read/write | 00h with PUC | Section 26.4.2 |
112h | SD16MEM0 | SD16_A conversion memory | Read/write | 00h with PUC | Section 26.4.3 |
B0h | SD16INCTL0 | SD16_A input control | Read/write | 00h with PUC | Section 26.4.4 |
B7h | SD16AE | SD16_A analog enable | Read/write | 00h with PUC | Section 26.4.5 |
110h | SD16IV | SD16_A interrupt vector | Read/write | 00h with PUC | Section 26.4.6 |
SD16_A Control Register
SD16CTL is shown in Figure 26-9 and described in Table 26-6.
Return to Table 26-5.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Reserved | SD16XDIVx | SD16LP | |||||
r0 | r0 | r0 | r0 | rw-0 | rw-0 | rw-0 | rw-0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SD16DIVx | SD16SSELx | SD16VMIDON | SD16REFON | SD16OVIE | Reserved | ||
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | r0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | Reserved | R | 0h | |
11-9 | SD16XDIVx | R/W | 0h | SD16_A clock divider 000b = /1 001b = /3 010b = /16 011b = /48 1xxb = Reserved |
8 | SD16LP | R/W | 0h | Low-power mode. This bit selects a reduced-speed reduced-power mode. 0b = Low-power mode is disabled 1b = Low-power mode is enabled. The maximum clock frequency for the SD16_A is reduced. |
7-6 | SD16DIVx | R/W | 0h | SD16_A clock divider 00b = /1 01b = /2 10b = /4 11b = /8 |
5-4 | SD16SSELx | R/W | 0h | SD16_A clock source select 00b = MCLK 01b = SMCLK 10b = ACLK 11b = External TACLK |
3 | SD16VMIDON | R/W | 0h | VMID buffer on 0b = Off 1b = On |
2 | SD16REFON | R/W | 0h | Reference generator on 0b = Reference off 1b = Reference on |
1 | SD16OVIE | R/W | 0h | SD16_A overflow interrupt enable. The GIE bit must also be set to enable the interrupt. 0b = Overflow interrupt disabled 1b = Overflow interrupt enabled |
0 | Reserved | R | 0h |
SD16_A Channel 0 Control Register
SD16CCTL0 is shown in Figure 26-10 and described in Table 26-7.
Return to Table 26-5.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Reserved | SD16BUFx#SLAU144SD16AR316 | SD16UNI | SD16XOSR | SD16SNGL | SD16OSRx | ||
r0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SD16LSBTOG | SD16LSBACC | SD16OVIFG | SD16DF | SD16IE | SD16IFG | SD16SC | Reserved |
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | r-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | Reserved | R | 0h | |
14-13 | SD16BUFx#SLAU144SD16AR316 | R/W | 0h | High-impedance input buffer mode. Reserved in MSP430x20x3 devices 00b = Buffer disabled 01b = Low speed and current 10b = Medium speed and current 11b = High speed and current |
12 | SD16UNI | R/W | 0h | Unipolar mode select 0b = Bipolar mode 1b = Unipolar mode |
11 | SD16XOSR | R/W | 0h | Extended oversampling ratio. This bit, along with the SD16OSRx bits, select the oversampling ratio. See SD16OSRx bit description for settings. |
10 | SD16SNGL | R/W | 0h | Single conversion mode select 0b = Continuous conversion mode 1b = Single conversion mode |
9-8 | SD16OSRx | R/W | 0h | Oversampling ratio When SD16XOSR = 0 00b = 256 01b = 128 10b = 64 11b = 32 When SD16XOSR = 1 00b = 512 01b = 1024 10b = Reserved 11b = Reserved |
7 | SD16LSBTOG | R/W | 0h | LSB toggle. This bit, when set, causes SD16LSBACC to toggle each time the SD16MEM0 register is read. 0b = SD16LSBACC does not toggle with each SD16MEM0 read 1b = SD16LSBACC toggles with each SD16MEM0 read |
6 | SD16LSBACC | R/W | 0h | LSB access. This bit allows access to the upper or lower 16-bits of the SD16_A conversion result. 0b = SD16MEMx contains the most significant 16-bits of the conversion. 1b = SD16MEMx contains the least significant 16-bits of the conversion. |
5 | SD16OVIFG | R/W | 0h | SD16_A overflow interrupt flag 0b = No overflow interrupt pending 1b = Overflow interrupt pending |
4 | SD16DF | R/W | 0h | SD16_A data format 0b = Offset binary 1b = 2s complement |
3 | SD16IE | R/W | 0h | SD16_A interrupt enable 0b = Disabled 1b = Enabled |
2 | SD16IFG | R/W | 0h | SD16_A interrupt flag. SD16IFG is set when new conversion results are available. SD16IFG is automatically reset when the corresponding SD16MEMx register is read, or may be cleared with software. 0b = No interrupt pending 1b = Interrupt pending |
1 | SD16SC | R/W | 0h | SD16_A start conversion 0b = No conversion start 1b = Start conversion |
0 | Reserved | R | 0h |
SD16_A Conversion Memory Register
SD16MEM0 is shown in Figure 26-11 and described in Table 26-8.
Return to Table 26-5.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Conversion_Results | |||||||
r-0 | r-0 | r-0 | r-0 | r-0 | r-0 | r-0 | r-0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Conversion_Results | |||||||
r-0 | r-0 | r-0 | r-0 | r-0 | r-0 | r-0 | r-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | Conversion_Results | R | 0h | Conversion Results. The SD16MEMx register holds the upper or lower 16-bits of the digital filter output, depending on the SD16LSBACC bit. |
SD16_A Input Control Register
SD16INCTL0 is shown in Figure 26-12 and described in Table 26-9.
Return to Table 26-5.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SD16INTDLYx | SD16GAINx | SD16INCHx | |||||
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | SD16INTDLYx | R/W | 0h | Interrupt delay generation after conversion start. These bits select the delay for the first interrupt after conversion start. 00b = Fourth sample causes interrupt 01b = Third sample causes interrupt 10b = Second sample causes interrupt 11b = First sample causes interrupt |
5-3 | SD16GAINx | R/W | 0h | SD16_A preamplifier gain 000b = ×1 001b = ×2 010b = ×4 011b = ×8 100b = ×16 101b = ×32 110b = Reserved 111b = Reserved |
2-0 | SD16INCHx | R/W | 0h | SD16_A channel differential pair input 000b = A0 001b = A1 010b = A2 011b = A3 100b = A4 101b = A5, (AVCC – AVSS) / 11 110b = A6, Temperature sensor 111b = A7, Short for PGA offset measurement |
SD16_A Analog Enable Register
SD16AE is shown in Figure 26-13 and described in Table 26-10.
Return to Table 26-5.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SD16AE7 | SD16AE6 | SD16AE5 | SD16AE4 | SD16AE3 | SD16AE2 | SD16AE1 | SD16AE0 |
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SD16AE7 | R/W | 0h | SD16_A analog enable 7 0b = External input disabled. Negative inputs are internally connected to VSS. 1b = External input enabled. |
6 | SD16AE6 | R/W | 0h | SD16_A analog enable 6 0b = External input disabled. Negative inputs are internally connected to VSS. 1b = External input enabled. |
5 | SD16AE5 | R/W | 0h | SD16_A analog enable 5 0b = External input disabled. Negative inputs are internally connected to VSS. 1b = External input enabled. |
4 | SD16AE4 | R/W | 0h | SD16_A analog enable 4 0b = External input disabled. Negative inputs are internally connected to VSS. 1b = External input enabled. |
3 | SD16AE3 | R/W | 0h | SD16_A analog enable 3 0b = External input disabled. Negative inputs are internally connected to VSS. 1b = External input enabled. |
2 | SD16AE2 | R/W | 0h | SD16_A analog enable 2 0b = External input disabled. Negative inputs are internally connected to VSS. 1b = External input enabled. |
1 | SD16AE1 | R/W | 0h | SD16_A analog enable 1 0b = External input disabled. Negative inputs are internally connected to VSS. 1b = External input enabled. |
0 | SD16AE0 | R/W | 0h | SD16_A analog enable 0 0b = External input disabled. Negative inputs are internally connected to VSS. 1b = External input enabled. |
SD16_A Interrupt Vector Register
SD16IV is shown in Figure 26-14 and described in Table 26-11.
Return to Table 26-5.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SD16IVx | |||||||
r-0 | r-0 | r-0 | r-0 | r-0 | r-0 | r-0 | r-0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SD16IVx | |||||||
r-0 | r-0 | r-0 | r-0 | r-0 | r-0 | r-0 | r-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | SD16IVx | R | 0h | SD16_A interrupt vector value. See Table 26-12. |
SD16IV Contents | Interrupt Source | Interrupt Flag | Interrupt Priority |
---|---|---|---|
000h | No interrupt pending | – | |
002h | SD16MEMx overflow | SD16CCTLx SD16OVIFG | Highest |
004h | SD16_A interrupt | SD16CCTL0 SD16IFG | |
006h | Reserved | – | |
008h | Reserved | – | |
00Ah | Reserved | – | |
00Ch | Reserved | – | |
00Eh | Reserved | – | |
010h | Reserved | – | Lowest |