SLAU144K December 2004 – August 2022 MSP430AFE221 , MSP430AFE222 , MSP430AFE223 , MSP430AFE231 , MSP430AFE232 , MSP430AFE233 , MSP430AFE251 , MSP430AFE252 , MSP430AFE253 , MSP430F2001 , MSP430F2002 , MSP430F2003 , MSP430F2011 , MSP430F2012 , MSP430F2013 , MSP430F2101 , MSP430F2111 , MSP430F2112 , MSP430F2121 , MSP430F2122 , MSP430F2131 , MSP430F2132 , MSP430F2132-EP , MSP430F2232 , MSP430F2234 , MSP430F2252 , MSP430F2252-Q1 , MSP430F2254 , MSP430F2272 , MSP430F2272-Q1 , MSP430F2274 , MSP430F2274-EP , MSP430F233 , MSP430F2330 , MSP430F235 , MSP430F2350 , MSP430F2370 , MSP430F2410 , MSP430F2416 , MSP430F2417 , MSP430F2418 , MSP430F2419 , MSP430F247 , MSP430F2471 , MSP430F248 , MSP430F2481 , MSP430F249 , MSP430F2491 , MSP430F2616 , MSP430F2617 , MSP430F2618 , MSP430F2619 , MSP430G2001 , MSP430G2101 , MSP430G2102 , MSP430G2111 , MSP430G2112 , MSP430G2121 , MSP430G2131 , MSP430G2132 , MSP430G2152 , MSP430G2153 , MSP430G2201 , MSP430G2201-Q1 , MSP430G2202 , MSP430G2203 , MSP430G2210 , MSP430G2211 , MSP430G2212 , MSP430G2213 , MSP430G2221 , MSP430G2230 , MSP430G2231 , MSP430G2231-Q1 , MSP430G2232 , MSP430G2233 , MSP430G2252 , MSP430G2253 , MSP430G2302 , MSP430G2303 , MSP430G2312 , MSP430G2313 , MSP430G2332 , MSP430G2333 , MSP430G2352 , MSP430G2353 , MSP430G2402 , MSP430G2403 , MSP430G2412 , MSP430G2413 , MSP430G2432 , MSP430G2433 , MSP430G2444 , MSP430G2452 , MSP430G2453 , MSP430G2513 , MSP430G2533 , MSP430G2544 , MSP430G2553 , MSP430G2744 , MSP430G2755 , MSP430G2855 , MSP430G2955 , MSP430TCH5E
Table 20-7 lists the memory-mapped registers for the OA.
Address | Acronym | Register Name | Type | Reset | Section |
---|---|---|---|---|---|
C0h | OA0CTL0 | OA0 control 0 | Read/write | 00h with POR | Section 20.4.1 |
C1h | OA0CTL1 | OA0 control 1 | Read/write | 00h with POR | Section 20.4.2 |
C2h | OA1CTL0 | OA1 control 0 | Read/write | 00h with POR | Section 20.4.1 |
C3h | OA1CTL1 | OA1 control 1 | Read/write | 00h with POR | Section 20.4.2 |
C4h | OA2CTL0 | OA2 control 0 | Read/write | 00h with POR | Section 20.4.1 |
C5h | OA2CTL1 | OA2 control 1 | Read/write | 00h with POR | Section 20.4.2 |
OAx Control 0 Register
OAxCTL0 is shown in Figure 20-6 and described in Table 20-8.
Return to Table 20-7.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OANx | OAPx | OAPMx | OAADCx | ||||
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | OANx | R/W | 0h | Inverting input select. These bits select the input signal for the OA inverting input. 00b = OAxI0 01b = OAxI1 10b = OAxIA (see the device-specific data sheet for connected signal) 11b = OAxIB (see the device-specific data sheet for connected signal) |
5-4 | OAPx | R/W | 0h | Noninverting input select. These bits select the input signal for the OA noninverting input. 00b = OAxI0 01b = OA0I1 10b = OAxIA (see the device-specific data sheet for connected signal) 11b = OAxIB (see the device-specific data sheet for connected signal) |
3-2 | OAPMx | R/W | 0h | Slew rate select. These bits select the slew rate vs. current consumption for the OA. 00b = Off, output high Z 01b = Slow 10b = Medium 11b = Fast |
1-0 | OAADCx | R/W | 0h | OA output select. These bits, together with the OAFCx bits, control the routing of the OAx output when OAPMx > 0. When OAFCx = 0: 00b = OAxOUT connected to external pins and ADC input A1, A3, or A5 01b = OAxOUT connected to external pins and ADC input A12, A13, or A14 10b = OAxOUT connected to external pins and ADC input A1, A3, or A5 11b = OAxOUT connected to external pins and ADC input A12, A13, or A14 When OAFCx > 0: 00b = OAxOUT used for internal routing only 01b = OAxOUT connected to external pins and ADC input A12, A13, or A14 10b = OAxOUT connected to external pins and ADC input A1, A3, or A5 11b = OAxOUT connected internally to ADC input A12, A13, or A14. External A12, A13, or A14 pin connections are disconnected from the ADC. |
OAx Control 1 Register
OAxCTL1 is shown in Figure 20-7 and described in Table 20-9.
Return to Table 20-7.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OAFBRx | OAFCx | OANEXT | OARRIP | ||||
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | OAFBRx | R/W | 0h | OAx feedback resistor select. 000b = Tap 0: 0R/16R 001b = Tap 1: 4R/12R 010b = Tap 2: 8R/8R 011b = Tap 3: 10R/6R 100b = Tap 4: 12R/4R 101b = Tap 5: 13R/3R 110b = Tap 6: 14R/2R 111b = Tap 7: 15R/1R |
4-2 | OAFCx | R/W | 0h | OAx function control. This bit selects the function of OAx. 000b = General-purpose opamp 001b = Unity gain buffer for three-opamp differential amplifier 010b = Unity gain buffer 011b = Comparator 100b = Noninverting PGA amplifier 101b = Cascaded noninverting PGA amplifier 110b = Inverting PGA amplifier 111b = Differential amplifier |
1 | OANEXT | R/W | 0h | OAx inverting input externally available. This bit, when set, connects the inverting OAx input to the external pin when the integrated resistor network is used. 0b = OAx inverting input not externally available 1b = OAx inverting input externally available |
0 | OARRIP | R/W | 0h | OAx reverse resistor connection in comparator mode. 0b = RTOP is connected to AVSS and RBOTTOM is connected to AVCC when OAFCx = 3 1b = RTOP is connected to AVCC and RBOTTOM is connected to AVSS when OAFCx = 3. |