9.6.4 AES_DMAIC Register (Offset = 0x2C) [reset = 0x0]
AES DMA Interrupt Clear (AES_DMAIC)
The AES DMA Interrupt Clear (AES_DMAIC) register is used to clear the AES_DMARIS and AES_DMAMIS registers by writing a 1 to each register bit.
NOTE
This registers always reads as zero.
AES_DMAIC is shown in Figure 9-30 and described in Table 9-26.
Return to Summary Table.
Figure 9-30 AES_DMAIC Register
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
RESERVED |
R-0x0 |
|
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
RESERVED |
R-0x0 |
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
RESERVED |
R-0x0 |
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
RESERVED |
DOUT |
DIN |
COUT |
CIN |
R-0x0 |
W1C-0x0 |
W1C-0x0 |
W1C-0x0 |
W1C-0x0 |
|
Table 9-26 AES_DMAIC Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
31-4 |
RESERVED |
R |
0x0 |
|
3 |
DOUT |
W1C |
0x0 |
Data Out DMA Done Interrupt Clear.
Writing a 1 to this bit clears the DOUT bit in the AES_DMARIS and AES_DMAMIS register. |
2 |
DIN |
W1C |
0x0 |
Data In DMA Done Interrupt Clear.
Writing a 1 to this bit clears the DIN bit in the AES_DMARIS and AES_DMAMIS register. |
1 |
COUT |
W1C |
0x0 |
Context Out DMA Done Masked Interrupt Status.
Writing a 1 to this bit clears the COUT bit in the AES_DMARIS and AES_DMAMIS register. |
0 |
CIN |
W1C |
0x0 |
Context In DMA Done Raw Interrupt Status.
Writing a 1 to this bit clears the CIN bit in the AES_DMARIS and AES_DMAMIS register. |