SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
According to the IEEE 1588 specifications, a timestamp must be captured at the SFD of the transmitted and received frames at the MAC interface. Because the reference timing source, MOSC, is taken as different from MAC reference clocks, a small error margin is introduced, because of the transfer of information across asynchronous clock domains. In the transmit path, the captured and reported timestamp has a maximum error margin of 2 PTP (MOSC) clocks. It means that the captured timestamp has the reference timing source (MOSC) value that is given within 2 clocks after the SFD has been transmitted to the PHY. Similarly, in the receive path, the error margin is 3 MAC reference clocks, plus up to 2 PTP clocks. The error margin of the three MAC reference clocks can be ignored by assuming that this constant delay is present in the system (or link) before the SFD data reaches the interface of MAC.
NOTE
When the Ethernet Controller is configured to use the MII interface to an external PHY, the MII clock is provided by the external PHY through EN0RXCK and EN0TXCK. When the Ethernet Controller is connected to the integrated PHY, the reference clock must be 25 MHz because it is also the source to the PHY.
NOTE
When IEEE 1588 timestamping is enabled with internal timestamp, use a PTP clock frequency that is greater than 5 MHz. This is because the SSINC field in the EMACSUBSECINC register limits the PTP frequency that can be used to approximately 4 MHz.