SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Ethernet PHY Specific Control- MR17 (EPHYSCR)
This register implements the PHY Specific Control register. This register allows access to general functionality inside the PHY to enable operation in reduced power modes and control the interrupt mechanism.
EPHYSCR is shown in Figure 15-104 and described in Table 15-116.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DISCLK | PSEN | PSMODE | SBPYASS | RESERVED | LBFIFO | ||
R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x1 | R-0x0 | R/W-0x0 | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COLFDM | RESERVED | TINT | INTEN | RESERVED | ||
R-0x0 | R/W-0x0 | R-0x0 | R/W-0x0 | R/W-0x1 | R-0x0 | ||