| 31-14 |
RESERVED |
R |
0x0 |
|
| 13 |
PROGRIS |
R |
0x0 |
Program Verify Error Raw Interrupt Status
This bit is cleared by writing a 1 to the PROGMISC bit in the FCMISC register.
0x0 = An interrupt has not occurred.
0x1 = An interrupt is pending because the verify of a PROGRAM operation failed. If this error occurs when using the Flash write buffer, software must inspect the affected words to determine where the error occurred.
|
| 12 |
RESERVED |
R |
0x0 |
|
| 11 |
ERRIS |
R |
0x0 |
Erase Verify Error Raw Interrupt Status
This bit is cleared by writing a 1 to the ERMISC bit in the FCMISC register.
0x0 = An interrupt has not occurred.
0x1 = An interrupt is pending because the verify of an ERASE operation failed. If this error occurs when using the Flash write buffer, software must inspect the affected words to determine where the error occurred.
|
| 10 |
INVDRIS |
R |
0x0 |
Invalid Data Raw Interrupt Status
This bit is cleared by writing a 1 to the INVMISC bit in the FCMISC register.
0x0 = An interrupt has not occurred.
0x1 = An interrupt is pending because a bit that was previously programmed as a 0 is now being requested to be programmed as a 1.
|
| 9 |
VOLTRIS |
R |
0x0 |
Pump Voltage Raw Interrupt Status
This bit is cleared by writing a 1 to the VOLTMISC bit in the FCMISC register.
0x0 = An interrupt has not occurred.
0x1 = An interrupt is pending because the regulated voltage of the pump went out of spec during the Flash operation and the operation was terminated.
|
| 8-3 |
RESERVED |
R |
0x0 |
|
| 2 |
ERIS |
R |
0x0 |
EEPROM Raw Interrupt Status
This bit provides status EEPROM operation.
This bit is cleared by writing a 1 to the EMISC bit in the FCMISC register.
0x0 = An EEPROM interrupt has not occurred.
0x1 = An EEPROM interrupt has occurred.
|
| 1 |
PRIS |
R |
0x0 |
Programming Raw Interrupt Status
This bit provides status on programming cycles which are write or erase actions generated through the FMC or FMC2 register bits (see and ).
This status is sent to the interrupt controller when the PMASK bit in the FCIM register is set.
This bit is cleared by writing a 1 to the PMISC bit in the FCMISC register.
0x0 = The programming or erase cycle has not completed.
0x1 = The programming or erase cycle has completed.
|
| 0 |
ARIS |
R |
0x0 |
Access Raw Interrupt Status
This status is sent to the interrupt controller when the AMASK bit in the FCIM register is set.
This bit is cleared by writing a 1 to the AMISC bit in the FCMISC register.
0x0 = No access has tried to improperly program or erase the Flash memory.
0x1 = A program or erase action was attempted on a block of Flash memory that contradicts the protection policy for that block as set in the FMPPEn registers.
|