31 |
WRC |
R |
0x1 |
Write Complete/Capable
Software must poll this bit between write requests and defer writes until WRC =1 to ensure proper operation.
An interrupt can be configured to indicate the WRC has completed.
The bit name WRC means "Write Complete," which is the normal use of the bit (between write accesses).
However, because the bit is set out-of-reset, the name can also mean "Write Capable" which simply indicates that the interface may be written to by software.
This difference may be exploited by software at reset time to detect which method of programming is appropriate:
0 = software delay loops required
1 = WRC paced available.
0x0 = The interface is processing a prior write and is busy. Any write operation that is attempted while WRC is 0 results in undetermined behavior.
0x1 = The interface is ready to accept a write.
|
30 |
RETCLR |
R/W |
0x0 |
GPIO Retention/Clear
This bit is used when the VDD3ON bit is set.
This bit is must be set when entering the hibernate state when the VDD3ON bit is set.
This does not affect behavior when VDD3ON is clear.
This bit must be set when enabling VDD3ON mode.
0x0 = GPIO retention is released when power is reapplied. The GPIOs are initialized to default values.
0x1 = GPIO retention set until software clears this bit.
|
29-20 |
RESERVED |
R |
0x0 |
|
19 |
OSCSEL |
R/W |
0x0 |
Oscillator Select
This bit is used to select between the use of an external 32.
768-kHz source or the HIB internal low frequency oscillator (HIB LFIOSC).
To enable the HIB LFIOSC, CLK32EN must be programmed to 1 at the same time the OSCSEL bit is set.
Thus the HIBCTL register should be written with 0x00080040 The HIB low-frequency oscillator has a wide frequency variation, therefore the RTC is not accurate when using this clock source.
0x0 = External 32.786-kHZ clock source is enabled.
0x1 = HIB Low frequency oscillator (HIB LFIOSC) is enabled.
|
18 |
RESERVED |
R |
0x0 |
|
17 |
OSCDRV |
R/W |
0x0 |
Oscillator Drive Capability
This bit is used to compensate for larger or smaller filtering capacitors.
This bit is not meant to be changed once the Hibernation oscillator has started.
Oscillator stability is not guaranteed if the user changes this value after the oscillator is running.
0x0 = Low drive strength is enabled, 12 pF.
0x1 = High drive strength is enabled, 24 pF.
|
16 |
OSCBYP |
R/W |
0x0 |
Oscillator Bypass
0x0 = The internal 32.768-kHz Hibernation oscillator is enabled. This bit should be cleared when using an external 32.768-kHz crystal.
0x1 = The internal 32.768-kHz Hibernation oscillator is disabled and powered down. This bit should be set when using a single-ended oscillator attached to XOSC0.
|
15 |
RESERVED |
R |
0x0 |
|
14-13 |
VBATSEL |
R/W |
0x1 |
Select for Low-Battery Comparator
This field selects the battery level that is used when checking the battery status.
If the battery voltage is below the specified level, the LOWBAT interrupt bit in the HIBRIS register is set.
0x0 = 1.9 Volts
0x1 = 2.1 Volts (default)
0x2 = 2.3 Volts
0x3 = 2.5 Volts
|
12-11 |
RESERVED |
R |
0x0 |
|
10 |
BATCHK |
R/W |
0x0 |
Check Battery Status
0x0 = When read, indicates that the low-battery comparator cycle is not active.Writing a 0 has no effect.
0x1 = When read, indicates the low-battery comparator cycle has not completed.Setting this bit initiates a low-battery comparator cycle. If the battery voltage is below the level specified by VBATSEL field, the LOWBAT interrupt bit in the HIBRIS register is set. A hibernation request is held off if a battery check is in progress.
|
9 |
BATWKEN |
R/W |
0x0 |
Wake on Low Battery
0x0 = The battery voltage level is not automatically checked. Low battery voltage does not cause the microcontroller to wake from hibernation.
0x1 = In RTC mode, w hen this bit is set, the battery voltage level is checked every 512 seconds while in hibernation.In calendar mode, the battery voltage is checked on minutes divisible by 8 while in hibernation. If the voltage is below the level specified by VBATSEL field, the microcontroller wakes from hibernation and the LOWBAT interrupt bit in the HIBRIS register is set.
|
8 |
VDD3ON |
R/W |
0x0 |
VDD Powered
Regardless of the status of the VDD3ON bit, the HIB signal is asserted during Hibernate mode.
Thus, when VDD3ON is set, the HIB signal should not be connected to the 3.3V regulator, and the 3.3V power source should remain connected.
When this bit is set while in hibernation, all pins are held in the state they were in prior to entering hibernation.
For example, inputs remain inputs
outputs driven high remain driven high, and so on.
Ports retain their state in VDD3ON mode until the RETCLR bit is cleared.
The RETCLR bit must be set when the VDD3ON bit is set.
0x0 = The internal switches are not used. The HIB signal should be used to control an external switch or regulator.
0x1 = The internal switches control the power to the on-chip modules (VDD3ON mode).
|
7 |
VABORT |
R/W |
0x0 |
Power Cut Abort Enable
0x0 = The microcontroller goes into hibernation regardless of the voltage level of the battery.
0x1 = When this bit is set, the battery voltage level is checked before entering hibernation. If VBATis less than the voltage specified by VBATSEL, the microcontroller does not go into hibernation.
|
6 |
CLK32EN |
R/W |
0x0 |
Clocking Enable
This bit must be enabled to use the Hibernation module.
0x0 = The Hibernation module clock source is disabled.
0x1 = The Hibernation module clock source is enabled.
|
5 |
RESERVED |
R |
0x0 |
|
4 |
PINWEN |
R/W |
0x0 |
External Wake and Interrupt Pin Enable
The external I/O wake pad interrupt is set if the WAKE pin is asserted in Run, Sleep, or Deep Sleep mode regardless of whether the PINWEN bit is 0x0 or 0x1.
The interrupt may be forwarded to the processor by setting the EXTW bit in the HIBIM register.
0x0 = The status of the WAKE or an external I/O wake pad source pin has no effect on hibernation.
0x1 = An assertion of the WAKE pin or an external I/O wake pad source takes the microcontroller out of hibernation. An external I/O wake pad interrupt may be generated in active mode.
|
3 |
RTCWEN |
R/W |
0x0 |
RTC Wake-up Enable
0x0 = An RTC match event has no effect on hibernation.
0x1 = An RTC match event (the value the HIBRTCC register matches the value of the HIBRTCM0 register and the value of the RTCSSC field matches the RTCSSM field in the HIBRTCSS register) takes the microcontroller out of hibernation.
|
2 |
RESERVED |
R |
0x0 |
|
1 |
HIBREQ |
R/W |
0x0 |
Hibernation Request
After a wake-up event, this bit is automatically cleared by hardware.
A hibernation request is ignored if both the PINWEN and RTCWEN bits are clear.
0x0 = No hibernation request.
0x1 = Set this bit to initiate hibernation.
|
0 |
RTCEN |
R/W |
0x0 |
RTC Timer /Calendar Enable
This is bit must be set to enable RTC or calendar mode.
For calendar mode enable, the CALEN bit in the HIBCALCTL register must also be set.
The low-frequency oscillator has a wide frequency variation, therefore the RTC is not accurate when using this clock source.
0x0 = The Hibernation module RTC and calendar mode are disabled.
0x1 = The Hibernation module RTC and calendar mode are enabled.
|