6.5.8 HIBIC Register (Offset = 0x20) [reset = 0x0]
Hibernation Interrupt Clear (HIBIC)
This register is the interrupt write-one-to-clear register for the Hibernation module interrupt sources. Writing a 1 to a bit clears the corresponding interrupt in the HIBRIS register.
NOTE
Writes to the RSTWK, PADIOWK and WC bits of this register are immediate and the status may be read from the HIBRIS and HIBMIS registers without monitoring the WRC bit of the HIBCTL register.
NOTE
All I/O wake sources are cleared by a write to either or both the RSTWK and PADIOWK bits. This clears the source of interrupts for RSTWK, PADIOWK and the GPIOWAKESTAT register.
HIBIC is shown in Figure 6-16 and described in Table 6-11.
Return to Summary Table.
Figure 6-16 HIBIC Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| VDDFAIL |
RSTWK |
PADIOWK |
WC |
EXTW |
LOWBAT |
RESERVED |
RTCALT0 |
| R/W1C-0x0 |
R/W1C-0x0 |
R/W1C-0x0 |
R/W1C-0x0 |
R/W1C-0x0 |
R/W1C-0x0 |
R-0x0 |
R/W1C-0x0 |
|
Table 6-11 HIBIC Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-8 |
RESERVED |
R |
0x0 |
|
| 7 |
VDDFAIL |
R/W1C |
0x0 |
VDD Fail Interrupt Clear
Writing a 1 to this bit clears the VDDFAIL bit in the HIBRIS and HIBMIS registers.
Reads return the raw interrupt status. |
| 6 |
RSTWK |
R/W1C |
0x0 |
Reset Pad I/O Wake-Up Interrupt Clear Writing a 1 to this bit clears the RSTWK bit in the HIBRIS and HIBMIS registers.
Reads return the raw interrupt status. |
| 5 |
PADIOWK |
R/W1C |
0x0 |
Pad I/O Wake-Up Interrupt Clear Writing a 1 to this bit clears the PADIOWK bit in the HIBRIS and HIBMIS registers.
Reads return the raw interrupt status. |
| 4 |
WC |
R/W1C |
0x0 |
Write Complete/Capable Interrupt Clear
Writing a 1 to this bit clears the WC bit in the HIBRIS and HIBMIS registers.
Reads return the raw interrupt status. |
| 3 |
EXTW |
R/W1C |
0x0 |
External Wake-Up Interrupt Clear
Writing a 1 to this bit clears the EXTW bit in the HIBRIS and HIBMIS registers.
Reads return the raw interrupt status. |
| 2 |
LOWBAT |
R/W1C |
0x0 |
Low Battery Voltage Interrupt Clear
Writing a 1 to this bit clears the LOWBAT bit in the HIBRIS and HIBMIS registers.
Reads return the raw interrupt status. |
| 1 |
RESERVED |
R |
0x0 |
|
| 0 |
RTCALT0 |
R/W1C |
0x0 |
RTC Alert0 Masked Interrupt Clear
Writing a 1 to this bit clears the RTCALT0 bit in the HIBRIS and HIBMIS registers.
Reads return the raw interrupt status.
The timer interrupt source cannot be cleared if the RTC value and the HIBRTCM0 register / RTCMSS field values are equal.
The match interrupt takes priority over the interrupt clear. |