6.5.7 HIBMIS Register (Offset = 0x1C) [reset = 0x0]
Hibernation Masked Interrupt Status (HIBMIS)
This register is the masked interrupt status for the Hibernation module interrupt sources. Bits in this register are the AND of the corresponding bits in the HIBRIS and HIBIM registers. When both corresponding bits are set, the bit in this register is set, and the interrupt is sent to the interrupt controller.
HIBMIS is shown in Figure 6-15 and described in Table 6-10.
Return to Summary Table.
Figure 6-15 HIBMIS Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| VDDFAIL |
RSTWK |
PADIOWK |
WC |
EXTW |
LOWBAT |
RESERVED |
RTCALT0 |
| R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
|
Table 6-10 HIBMIS Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-8 |
RESERVED |
R |
0x0 |
|
| 7 |
VDDFAIL |
R |
0x0 |
VDD Fail Interrupt Mask
0x0 = An VDDFAIL interrupt has not occurred or is masked.
0x1 = An unmasked interrupt was signaled due to a an arbitrary loss of power or because on or more of the voltage supplies (VDD, VDDA or VDDC) has dropped below the defined operating range.
|
| 6 |
RSTWK |
R |
0x0 |
Reset Pad I/O Wake-Up Interrupt Mask
0x0 = An external reset interrupt has not occurred or is masked.
0x1 = An unmasked interrupt was signaled due to a RESET pin assertion.
|
| 5 |
PADIOWK |
R |
0x0 |
Pad I/O Wake-Up Interrupt Mask
0x0 = An external GPIO or reset interrupt has not occurred or is masked.
0x1 = An unmasked interrupt was signaled due to a wake-enabled GPIO or RESET pin assertion.
|
| 4 |
WC |
R |
0x0 |
Write Complete/Capable Masked Interrupt Status
This bit is cleared by writing a 1 to the WC bit in the HIBIC register.
0x0 = The WRC bit has not been set or the interrupt is masked.
0x1 = An unmasked interrupt was signaled due to the WRC bit being set.
|
| 3 |
EXTW |
R |
0x0 |
External Wake-Up Masked Interrupt Status
This bit is cleared by writing a 1 to the EXTW bit in the HIBIC register.
0x0 = An external wake-up interrupt has not occurred or is masked.
0x1 = An unmasked interrupt was signaled due to a WAKE pin assertion.
|
| 2 |
LOWBAT |
R |
0x0 |
Low Battery Voltage Masked Interrupt Status
This bit is cleared by writing a 1 to the LOWBAT bit in the HIBIC register.
0x0 = A low-battery voltage interrupt has not occurred or is masked.
0x1 = An unmasked interrupt was signaled due to a low-battery voltage condition.
|
| 1 |
RESERVED |
R |
0x0 |
|
| 0 |
RTCALT0 |
R |
0x0 |
RTC Alert 0 Masked Interrupt Status
The MIS may apply to either the RTC or calendar block depending on which is enabled.
This bit is cleared by writing a 1 to the RTCALT0 bit in the HIBIC register.
0x0 = An RTC or calendar match interrupt has not occurred or is masked.
0x1 = An unmasked interrupt was signaled due to an RTC or calendar match.
|