31-8 |
RESERVED |
R |
0x0 |
|
7 |
VDDFAIL |
R |
0x0 |
VDD Fail Raw Interrupt Status
0x0 = No VDDFAIL interrupt condition exists.
0x1 = An interrupt is sent to the interrupt controller because of arbitrary power removal or because one or more of the supplies (VDD, VDDA or VDDC) has dropped below the defined operating range.
|
6 |
RSTWK |
R |
0x0 |
Reset Pad I/O Wake-Up Raw Interrupt Status
0x0 = The RESET pin has not been asserted or has not been enabled to wake the device from hibernation.
0x1 = An interrupt is sent to the interrupt controller because the RESET pin has been programmed to wake the device from hibernation.
|
5 |
PADIOWK |
R |
0x0 |
Pad I/O Wake-Up Raw Interrupt Status
0x0 = One of the wake-enabled GPIO pins or the external RESET pin has not been asserted or has not been enabled to wake the device from hibernation.
0x1 = An interrupt is sent to the interrupt controller because one of the wake-enabled GPIO pins or the external RESET pin has been asserted.
|
4 |
WC |
R |
0x0 |
Write Complete/Capable Raw Interrupt Status
This bit is cleared by writing a 1 to the WC bit in the HIBIC register.
0x0 = The WRC bit in the HIBCTL has not been set.
0x1 = The WRC bit in the HIBCTL has been set.
|
3 |
EXTW |
R |
0x0 |
External Wake-Up Raw Interrupt Status
A wake signal source must be cleared by the application after the interrupt has been registered.
This bit is cleared by writing a 1 to the EXTW bit in the HIBIC register.
The EXTW bit is set if the WAKE pin is asserted in any mode of operation (Run, Sleep, Deep Sleep) regardless of whether the PINWEN bit is set in the HIBCTL register.
0x0 = The WAKE pin has not been asserted.
0x1 = The WAKE pin has been asserted.
|
2 |
LOWBAT |
R |
0x0 |
Low Battery Voltage Raw Interrupt Status
This bit is cleared by writing a 1 to the LOWBAT bit in the HIBIC register.
0x0 = The battery voltage has not dropped below VLOWBAT.
0x1 = The battery voltage dropped below VLOWBAT.
|
1 |
RESERVED |
R |
0x0 |
|
0 |
RTCALT0 |
R |
0x0 |
RTC Alert 0 Raw Interrupt Status
This bit is cleared by writing a 1 to the RTCALT0 bit in the HIBIC register.
0x0 = No match
0x1 = If the RTC is enabled, t he value of the HIBRTCC register matches the value in the HIBRTCM0 register and the value of the RTCSSC field matches the RTCSSM field in the HIBRTCSS register.If the Calendar function is enabled, this interrupt status indicates that one or more of the allowed fields in the HIBCAL0/1 register matches in the HIBCALM0/1 register..
|