SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
I2C Master Control/Status (I2CMCS)
This register accesses status bits when read and control bits when written. When read, the status register indicates the state of the I2C bus controller. When written, the control register configures the I2C controller operation.
The START bit generates the START or repeated START condition. The STOP bit determines if the cycle stops at the end of the data cycle or continues to the next transfer cycle, which could be a repeated START. To generate a single transmit cycle, the I2CMSA register is written with the desired address, the R/S bit is cleared, and this register is written with ACK = X (0 or 1), STOP = 1, START = 1, and RUN = 1 to perform the operation and stop. When the operation is completed (or aborted due an error), an interrupt becomes active and the data may be read from the I2CMDR register. When the I2C module operates in master receiver mode, the ACK bit is normally set, causing the I2C bus controller to transmit an acknowledge automatically after each byte. This bit must be cleared when the I2C bus controller requires no further data to be transmitted from the slave transmitter.
NOTE
After the CPU starts a transaction, up to 60% of the I2C clock period is required before the BUSY bit is set. Therefore, a delay is required before reading this bit.
NOTE
When reading the I2CMCS register to check the BUSY bit, also read the ADRACK and DATACK bits, because these are cleared on register read, and status may be lost if they are not checked on every read of the register.
Alternatively, the NACKRIS bit of the I2CMRIS register can be used to monitor NACK status.
I2CMCS as a read-only status register is shown in Figure 19-17 and described in Table 19-6.
I2CMCS as a write-only control register is shown in Figure 19-18 and described in Table 19-7.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ACTDMARX | ACTDMATX | RESERVED | |||||
R-0x0 | R-0x0 | R-0x0 | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0x0 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLKTO | BUSBSY | IDLE | ARBLST | DATACK | ADRACK | ERROR | BUSY |
R-0x0 | R-0x0 | R-0x1 | R-0x0 | R-0x0 | R-0x0 | R-0x0 | R-0x0 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0x0 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0x0 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BURST | QCMD | HS | ACK | STOP | START | RUN |
R-0x0 | W-0x0 | W-0x0 | W-0x0 | W-0x0 | W-0x0 | W-0x0 | W-0x0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | RESERVED | R | 0x0 |
|
6 | BURST | W | 0x0 |
Burst Enable. The BURST and RUN bits are mutually exclusive. 0 = Burst operation is disabled. 1 = The master is enabled to burst using the receive and transmit FIFOs (see Table 19-8). |
5 | QCMD | W | 0x0 |
Quick Command. 0 = Bus transaction is not a quick command. 1 = The bus transaction is a quick command. To execute a quick command, the START, STOP and RUN bits also need to be set. After the quick command is issued, the master generates a STOP. |
4 | HS | W | 0x0 |
High-Speed Enable. 0 = The master operates in Standard, Fast mode, or Fast mode plus as selected by using a value in the I2CMTPR register that results in an SCL frequency of 100 kbps for Standard mode, 400 kbps for Fast mode, or 1 Mpbs for Fast mode plus. 1 = The master operates in High-Speed mode with transmission speeds up to 3.33 Mbps. |
3 | ACK | W | 0x0 |
Data Acknowledge Enable. 0 = The received data byte is not acknowledged automatically by the master. 1 = The received data byte is acknowledged automatically by the master (see Table 19-8). |
2 | STOP | W | 0x0 |
Generate STOP. 0 = The controller does not generate the STOP condition. 1 = The controller generates the STOP condition (see Table 19-8). |
1 | START | W | 0x0 |
Generate START. 0 = The controller does not generate the START condition. 1 = The controller generates the START or repeated START condition (see Table 19-8). |
0 | RUN | W | 0x0 |
I2C Master Enable. The BURST and RUN bits are mutually exclusive. 0 = In standard and high speed mode, this encoding means the master is unable to transmit or receive data. In Burst mode, this bit is not used and must be set to 0. 1 = The master is able to transmit or receive data. Note that this bit cannot be set in Burst mode (see Table 19-8). |
Table 19-8 can be read from left to right to determine the next state after programming bits in the I2CMSA and I2CMCS registers.
Current State | I2CMSA[0] | I2CMCS[6:0] | Next State Description | ||||||
---|---|---|---|---|---|---|---|---|---|
R/S | BURST | QCCMD | HS | ACK | STOP | START | RUN | ||
Idle | 0 | 0 | 0 | 0 | X(1) | 0 | 1 | 1 | START condition followed by TRANSMIT (master enters to the Master Transmit status). |
0 | 0 | 0 | 0 | X | 1 | 1 | 1 | START condition followed by a TRANSMIT and STOP condition (master remains in Idle status). | |
0 | 1 | 0 | 0 | X | 0 | 1 | 0 | START condition followed by N FIFO-serviced TRANSMITs (master goes to the Master Transmit status). | |
0 | 1 | 0 | 0 | X | 1 | 1 | 0 | START condition followed by N FIFO-serviced TRANSMITs and STOP condition (master remains in Idle status). | |
1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | START condition followed by RECEIVE operation with negative ACK (master goes to the Master Receive status). | |
0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | Quick Command (Send). After Quick Command is executed, the master returns to Idle status. | |
1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | Quick Command (Receive). After Quick Command is executed, the master returns to Idle status. | |
1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | START condition followed by RECEIVE and STOP condition (master remains in Idle status). | |
1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | START condition followed by RECEIVE (master goes to the Master Receivestatus). | |
1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | START condition followed by N FIFO-serviced RECEIVE operations with a negative ACK on the last RECEIVE operation (master goes to the Master Receive status). | |
1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | START condition followed by N FIFO-serviced RECEIVE operations with a negative ACK on the last RECEIVE and STOP condition (master remains in Idle status). | |
1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | START condition followed by N FIFO-serviced RECEIVE operations (master goes to the Master Receive status). | |
0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | START/RUN condition where master byte is sent with no ACK; followed by High Speed transmit Operation. All subsequent transfers are carried out using normal transmit commands. | |
0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | RUN/BURST condition where master byte is sent with no ACK; followed by High Speed Burst transmit Operation. | |
1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | Illegal | |
1 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | Illegal | |
All other combinations not listed are nonoperations. | NOP | ||||||||
Master Transmit | X | 0 | 0 | 0 | X | 0 | 0 | 1 | TRANSMIT operation (master remains in Master Transmit status). |
X | 0 | 0 | 0 | X | 1 | 0 | 0 | STOP condition (master goes to Idle status). | |
X | 0 | 0 | 0 | X | 1 | 0 | 1 | TRANSMIT followed by STOP condition (master goes to Idle status). | |
X | 1 | 0 | 0 | X | 0 | 0 | 0 | N FIFO-serviced TRANSMIT operations (master remains in Master Transmit status). | |
X | 1 | 0 | 0 | X | 1 | 0 | 0 | N FIFO-serviced TRANSMIT operations followed by STOP condition (master goes to Idle status). | |
0 | 0 | 0 | 0 | X | 0 | 1 | 1 | Repeated START condition followed by a TRANSMIT (master remains in Master Transmit status). | |
0 | 0 | 0 | 0 | X | 1 | 1 | 1 | Repeated START condition followed by TRANSMIT and STOP condition (master goes to Idle status). | |
0 | 1 | 0 | 0 | X | 0 | 1 | 0 | Repeated START condition followed by N FIFO-serviced TRANSMIT operations (master remains in Master Transmit status). | |
0 | 1 | 0 | 0 | X | 1 | 1 | 0 | Repeated START condition followed by N FIFO-serviced TRANSMIT operations and STOP condition (master goes to Idle status). | |
1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | Repeated START condition followed by a RECEIVE operation with a negative ACK (master goes to Master Receive status). | |
1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | Repeated START condition followed by a RECEIVE and STOP condition (master goes to Idle status). | |
1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | Repeated START condition followed by RECEIVE (master goes to Master Receive status). | |
1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | Repeated START condition followed by N FIFO-serviced RECEIVE operations with a negative ACK on the last RECEIVE operation (master goes to Master Receive status). | |
1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | Repeated START condition followed by N FIFO-serviced RECEIVE operations and STOP condition (master goes to Idle status). | |
1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | Repeated START condition followed by N FIFO-serviced RECEIVE operations (master goes to Master Receive status). | |
1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | Illegal | |
1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | Illegal | |
All other combinations not listed are nonoperations. | NOP | ||||||||
Master Receive | X | 0 | 0 | 0 | 0 | 0 | 0 | 1 | RECEIVE operation with negative ACK (master remains in Master Receive status). |
X | 0 | 0 | 0 | X | 1 | 0 | 0 | STOP condition (master goes to Idlestatus).(2) | |
X | 0 | 0 | 0 | 0 | 1 | 0 | 1 | RECEIVE followed by STOP condition (master goes to Idlestatus). | |
X | 0 | 0 | 0 | 1 | 0 | 0 | 1 | RECEIVE operation (master remains in Master Receivestatus). | |
X | 1 | 0 | 0 | 0 | 0 | 0 | 0 | N FIFO-serviced RECEIVE operations with negative ACK on the last RECEIVE (master remains in Master Receivestatus). | |
X | 1 | 0 | 0 | 0 | 1 | 0 | 0 | N FIFO-serviced RECEIVE operations followed by STOP condition (master goes to Idlestatus). | |
X | 1 | 0 | 0 | 1 | 0 | 0 | 0 | N FIFO-serviced RECEIVE operations (master remains in Master Receivestatus). | |
X | 0 | 0 | 0 | 1 | 1 | 0 | 1 | Illegal | |
X | 1 | 0 | 0 | 1 | 1 | 0 | 0 | Illegal | |
1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | Repeated START condition followed by RECEIVE operation with a negative ACK (master remains in Master Receivestatus). | |
1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | Repeated START condition followed by RECEIVE and STOP condition (master goes to Idlestatus). | |
1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | Repeated START condition followed by RECEIVE (master remains in Master Receivestatus). | |
1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | Repeated START condition followed by N FIFO-serviced RECEIVE operations with a negative ACK on the last RECEIVE (master remains in Master Receivestatus). | |
1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | Repeated START condition followed by N FIFO-serviced RECEIVE operations and STOP condition (master goes to Idlestatus). | |
1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | Repeated START condition followed by N FIFO-serviced RECEIVE operations (master remains in Master Receivestatus). | |
0 | 0 | 0 | 0 | X | 0 | 1 | 1 | Repeated START condition followed by TRANSMIT (master goes to Master Transmitstatus). | |
0 | 0 | 0 | 0 | X | 1 | 1 | 1 | Repeated START condition followed by TRANSMIT and STOP condition (master goes to Idlestatus). | |
0 | 1 | 0 | 0 | X | 0 | 1 | 0 | Repeated START condition followed by N FIFO-serviced TRANSMIT operations (master goes to Master Transmitstatus). | |
0 | 1 | 0 | 0 | X | 1 | 1 | 0 | Repeated START condition followed by N FIFO-serviced TRANSMIT operations and STOP condition (master goes to Idlestatus). | |
All other combinations not listed are nonoperations. | NOP |