20.3.4.1 Logical Data Path
The block diagram of the Raster controller is shown in Figure 20-1. Figure 20-3illustrates its logical data path for various operation modes (passive [STN] versus active [TFT] and various BPP size). Figure 20-3 shows that:
- The grayscaler and serializer and output FIFO blocks are bypassed in active (TFT) modes.
- The palette is bypassed in both 12- and 16-BPP modes.
In summary:
- The display image is stored in frame buffers.
- The built-in DMA engine constantly transfers the data stored in the frame buffers to the input FIFO.
- The Raster Controller relays data to the external pins according to the specified format.