SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
This section lists and describes the Memory Protection Unit (MPU) registers, in numerical order by address offset.
The MPU registers can only be accessed from privileged mode.
Table 2-41 lists the memory-mapped registers for the MPU. All register offset addresses not listed in Table 2-41 should be considered as reserved locations and the register contents should not be modified.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0xD90 | MPUTYPE | MPU Type | Section 2.6.1 |
| 0xD94 | MPUCTRL | MPU Control | Section 2.6.2 |
| 0xD98 | MPUNUMBER | MPU Region Number | Section 2.6.3 |
| 0xD9C | MPUBASE | MPU Region Base Address | Section 2.6.4 |
| 0xDA0 | MPUATTR | MPU Region Attribute and Size | Section 2.6.5 |
| 0xDA4 | MPUBASE1 | MPU Region Base Address 1 | Section 2.6.4 |
| 0xDA8 | MPUATTR1 | MPU Region Attribute and Size 1 | Section 2.6.5 |
| 0xDAC | MPUBASE2 | MPU Region Base Address 2 | Section 2.6.4 |
| 0xDB0 | MPUATTR2 | MPU Region Attribute and Size 2 | Section 2.6.5 |
| 0xDB4 | MPUBASE3 | MPU Region Base Address 3 | Section 2.6.4 |
| 0xDB8 | MPUATTR3 | MPU Region Attribute and Size 3 | Section 2.6.5 |
Complex bit access types are encoded to fit into small table cells. Table 2-42 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| WO | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |