SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Table 22-3 lists the memory-mapped registers for the OWIRE. All register offset addresses not listed in Table 22-3 should be considered as reserved locations and the register contents should not be modified.
The offsets are relative to the base address of the 1-Wire Master module: 0x400B6000.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0x0 | ONEWIRECS | 1-Wire Control and Status | Section 22.5.1 |
| 0x4 | ONEWIRETIM | 1-Wire Timing Override | Section 22.5.2 |
| 0x8 | ONEWIREDATW | 1-Wire Data Write | Section 22.5.3 |
| 0xC | ONEWIREDATR | 1-Wire Data Read | Section 22.5.4 |
| 0x100 | ONEWIREIM | 1-Wire Interrupt Mask | Section 22.5.5 |
| 0x104 | ONEWIRERIS | 1-Wire Raw Interrupt Status | Section 22.5.6 |
| 0x108 | ONEWIREMIS | 1-Wire Masked Interrupt Status | Section 22.5.7 |
| 0x10C | ONEWIREICR | 1-Wire Interrupt Clear | Section 22.5.8 |
| 0x120 | ONEWIREDMA | 1-Wire µDMA Control | Section 22.5.9 |
| 0xFC0 | ONEWIREPP | 1-Wire Peripheral Properties | Section 22.5.10 |
Complex bit access types are encoded to fit into small table cells. Table 22-4 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| W1C | 1C
W |
1 to clear
Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |