SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Table 24-1 lists the memory-mapped registers for the QEI. All register offset addresses not listed in Table 24-1 should be considered as reserved locations and the register contents should not be modified.
The offsets are relative to the base address of the QEI module: 0x4002C000.
The QEI module clock must be enabled before the registers can be programmed (see Section 4.2.100). There must be a delay of 3 system clocks after the QEI module clock is enabled before any QEI module registers are accessed.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0x0 | QEICTL | QEI Control | Section 24.5.1 |
0x4 | QEISTAT | QEI Status | Section 24.5.2 |
0x8 | QEIPOS | QEI Position | Section 24.5.3 |
0xC | QEIMAXPOS | QEI Maximum Position | Section 24.5.4 |
0x10 | QEILOAD | QEI Timer Load | Section 24.5.5 |
0x14 | QEITIME | QEI Timer | Section 24.5.6 |
0x18 | QEICOUNT | QEI Velocity Counter | Section 24.5.7 |
0x1C | QEISPEED | QEI Velocity | Section 24.5.8 |
0x20 | QEIINTEN | QEI Interrupt Enable | Section 24.5.9 |
0x24 | QEIRIS | QEI Raw Interrupt Status | Section 24.5.10 |
0x28 | QEIISC | QEI Interrupt Status and Clear | Section 24.5.11 |
Complex bit access types are encoded to fit into small table cells. Table 24-2 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
W1C | 1C
W |
1 to clear
Write |
Reset or Default Value | ||
-n | Value after reset or the default value |