SLLU369 july   2023 ISO6521

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Pin Configuration of the ISO6521 Device
    2. 2.2 EVM Board Block Diagram and Image
    3. 2.3 EVM Setup and Operation
  7. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials
  8. 4Additional Information
    1.     Trademarks

3.2 PCB Layouts

Figure 4-2 and Figure 4-4 shows the top and bottom views of the PCB layout of the EVM. Figure 4-3 shows the top layer of the EVM.

GUID-20230718-SS0I-QLXF-RNQS-QNB0CVJVBJPZ-low.svg Figure 3-2 ISO6521REUEVM PCB Layout - Composite Top View
GUID-20230718-SS0I-JC0G-4FHL-HLBGL4GN6DVG-low.svg Figure 3-3 ISO6521REUEVM PCB Layout - Top Layer
GUID-20230718-SS0I-HM0T-PJZL-PLTCC1RVPMLG-low.svg Figure 3-4 ISO6521REUEVM PCB Layout - Composite Bottom View