SLUA560D June 2011 – March 2022 UCC28950 , UCC28950-Q1 , UCC28951 , UCC28951-Q1
This application note presents a fixed delay approach to achieving ZVS from 100% load down to 50% load. When the converter is operating below 50% load the converter will be operating in valley switching. In order to achieve zero voltage switching on switch node of QBd, the turn-on (tABSET) delays of FETs QA and QB needs to be initially set based on the interaction of LS and the theoretical switch node capacitance. The following equations are used to set tABSET initially.
Equate shim inductance to two times COSS capacitance:
Calculate tank frequency:
Set initial tABSET delay time and adjust as necessary.
The 2.25 factor of the tABSET equation was derived from empirical test data and may vary based on individual design differences.
The resistor divider formed by RDA1 and RDA2 programs the tABSET, tCDSET delay range of the UCC28950/1. Select a standard resistor value for RDA1.
tABSET can be programmed between 30 ns to 1000 ns.
The voltage at the ADEL input of the UCC28950/1 (VADEL) needs to be set with RDA2 based on the following conditions.
If tABSET > 155 ns set VADEL = 0.2 V, tABSET can be programmed between 155 ns and 1000 ns:
If tABSET ≤ 155 ns set VADEL = 1.8 V, tABSET can be programmed between 29 ns and 155 ns:
Based on VADEL selection, calculate RDA2:
Select the closest standard resistor value for RDA2:
Recalculate VADEL based on resistor divider selection:
Resistor RDELAB programs tABSET:
Select a standard resistor value for the design:
Once you have a prototype up and running it is recommended you fine tune tABSET at light load to the peak and valley of the resonance between LS and the switch node capacitance. In this design the delay was set at 10% load.
The initial starting point for the QC and QD turn on delays (tCDSET) should be initially set for the same delay as the QA and QB turn on delays (Pin 6). The following equations program the QC and QD turn-on delays (tCDSET) by properly selecting resistor RDELCD (Pin 7).
Resistor RDELCD programs tCDSET:
Select a standard resistor for the design:
Once you have a prototype up and running it is recommended to fine tune tCDSET at light load. In this design the CD node was set to valley switch at roughly 10% load. Obtaining ZVS at lighter loads with switch node QDd is easier due to the reflected output current present in the primary of the transformer at FET QD and QC turnoff/on. This is because there was more peak current available to energize LS before this transition, compared to the QA and QB turnoff/on.
There is a programmable delay for the turnoff of FET QF after FET QA turnoff (tAFSET) and the turnoff of FET QE after FET QB turnoff (tBESET). A good place to set these delays is 50% of tABSET. This will ensure that the appropriate synchronous rectifier turns off before the AB ZVS transition. If this delay is too large it will cause OUTE and OUTF not to overlap correctly and it will create excess body diode conduction on FETs QE and QF.
The resistor divider formed by RCA1 and RCA2 programs the tAFSET and tBESET delay range of the UCC28950/1. Select a standard resistor value for RCA1.
tEFSET and tBESET can be programmed between 32 ns to 1100 ns.
The voltage at the ADELEF pin of the UCC28950/1 (VADELEF) needs to be set with RCA2 based on the following conditions.
If tAFSET < 170 ns set VADEL = 0.2 V, tABSET can be programmed between 32 ns and 170 ns:
If tABSET > or = 170 ns set VADEL = 1.7 V, tABSET can be programmed between 170 ns and 1100 ns:
Based on VADELEF selection, calculate RCA2:
Select the closest standard resistor value for RCA2:
Recalculate VADELEF based on resistor divider selection:
The following equation was used to program tAFSET and tBESET by properly selecting resistor RDELEF.
A standard resistor was chosen for the design.
Resistor RTMIN programs the minimum duty cycle on time (tMIN) that the UCC28950/1 (Pin 9) can demand before entering burst mode. If the UCC28950/1 controller tries to demand a duty cycle on time of less than tMIN the power supply will go into burst mode operation. Please see the UCC28950/1 data sheet for details regarding burst mode. For this design we set the minimum on time to 100 ns.
The minimum on time is set by selecting RTMIN with the following equation.
A standard resistor value is then chosen for the design.
There is a pin that is provided for setting up the converter switching frequency (Pin 10). The frequency can be selected by adjusting timing resistor RT.
Select a standard resistor for the design.