SLVAEV3A June   2020  – November 2022 TPS546D24A , TPS54824

 

  1.   Collection of DC/DC Buck Regulator Technical Documentation
  2.   Trademarks
  3. 1 Low Noise
  4. 2 Power Density
  5. 3 Thermals
  6. 4 Control-Mode Architectures
  7. 5 Powering Performance FPGAs, ASICs, and SoC
  8. 6 Light-Load and Full-Load Efficiency
  9. 7 Layout
  10. 8 Power Supply Topology
  11. 9 Packaging
  12. 10Revision History

9 Packaging

TI’s broad packaging portfolio supports thousands of diversified products, packaging configurations and technologies, including traditional ceramic and leaded options, to advanced chip scale packages (Quad Flat No Lead (QFN), Wafer Chip Scale Package (WCSP) or Die-Size Ball Grid Array (DSBGA)), using fine pitch wire bond and flip chip interconnects, with SiP, module, stacked and embedded die formats offered.

Table 9-1 Packaging-related Documentation
Document TitleLiterature Number
QFN/SON PCB AttachmentSLUA271B
PowerPAD™ Thermally Enhanced PackageSLMA002H
Benefits and Trade-offs of Various Power-Module Package OptionsSLYY120
HotRod™ QFN Package PCB AttachmentSLUA715
SMT Guidelines for Stacked Inductor (Inductor On Top) on Voltage Regulator ICSLVA764
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