The bq25890H allows each of the D+/D– lines to be controlled independently to output one of the preset voltage levels (0 V, 0.6 V, 1.2 V, 2.0 V, 2.7 V, 3.3 V, and HiZ). Each line can be set to one of these presets over I²C. This allows the implementation of a handshaking protocol between the charger and an adapter with an interface that allows adjusting the voltage, such as the CHY100 and CHY103 interfaces. Since the adapter voltage is controllable, the operating point of the charger can be fine-tuned to ensure high efficiency during charging. In addition, higher voltages allow enabling efficient high-charge currents. As a byproduct, charge time is decreased, making it even more appealing for high-capacity cells. REG01 of the bq25890H includes the bits needed to control the D+/D– output driver. The host processor can communicate through I 2 C to the charger, and modify this register to emulate the relevant adapter interface. This register also includes the bits to enable detection of HVDCP and MaxCharge adapters during the input current detection.

Figure 2-7 represents an example of how this behavior looks after implementing the increase or decrease functions, where Dx_y represents the specific D+ or D- thresholds based on the protocol used and ∆V, the resolution of the output voltage steps. D+/D- can generate multiple pulse signal periodicity through AP configuring. By adopting different D+ and D- pulse signal combination to increase or decrease output of adapter, for example, to adjust output power of adapter dynamically.