The board layout for the TPS54531EVM-530 is shown in Figure 5-1 through Figure 5-5. The top layer contains the main power traces for VIN, VOUT, and ground. Also on the top layer are connections for the pins of the TPS54531. Most of the signal traces also are located on the top side. The input decoupling capacitors (C1, C2, and C3) are located as close to the IC as possible. The input and output connectors, test points, and all of the components are located on the top side. An analog ground area is provided on the top side to terminate the sensitive compensation components (C7 and R3) and the output voltage feed back divider (R6). This ground area and the main power ground (GND) are connected at a single point on the top layer at the IC pin 7 (GND). The two internal layers are completely dedicated to power ground planes for heat dissipation. The bottom layer is primarily power ground with traces to connect the BOOT capacitor (C4) and the feedback trace from VOUT to the voltage set point divider network.

Figure 5-1 Top Assembly

Figure 5-2 Top Layer

Figure 5-3 Internal Layer 1

Figure 5-4 Internal Layer 2

Figure 5-5 Bottom Layer