SLVUCQ2A july   2023  – july 2023 TPSF12C1 , TPSF12C1-Q1

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications
    4. 1.4 Device Information
    5.     General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines
  8. 2Hardware
    1. 2.1 EVM Description
    2. 2.2 Setup
    3. 2.3 Header Information
    4. 2.4 EVM Performance Validation
    5. 2.5 AEF Design Flow
      1. 2.5.1 AEF Circuit Optimization and Debug
  9. 3Implementation Results
    1. 3.1 EMI Performance
    2. 3.2 Thermal Performance
    3. 3.3 Surge Immunity
    4. 3.4 SENSE and INJ Voltages
    5. 3.5 Insertion Loss
    6. 3.6 Passive vs. Active Solution Comparison
  10. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout
      1. 4.3.1 Assembly Drawings
      2. 4.3.2 Multi-Layer Stackup
  11. 5Compliance Information
    1. 5.1 Compliance and Certifications
  12. 6Additional Information
    1.     Trademarks
  13. 7Related Documentation
    1. 7.1 Supplemental Content
  14. 8Revision History

2.3 Header Information

Table 4-4, Table 3-2 and Table 3-3 detail the various signal headers installed on the EVM. In addition, SMB jacks designated J2, J3 and J4 on the PCB facilitate oscillator signal injection and frequency sweep for measurement of filter insertion loss or attenuation.

Header J1 specifically provides connections to the low-voltage side of the sense capacitors (corresponding to the SENSE pins of the TPSF12C1), the low-voltage side of the inject capacitor, the IC bias power supply (VDD and GND pins), which is set between 8 V and 16 V, and a remote enable (EN) signal.

Table 2-1 J1 Header Connections
POSITION(1) LABEL DESCRIPTION
1 EN Enable input – leave open or tie high to enable the IC; tie to GND to disable
2 VDD Supply voltage connection – connect to a 12-V bias power supply referenced to GND(2)
3 INJ Low-voltage terminal of the Y-rated inject capacitor, C10. Also connects to the AEF damping network
4 GND Ground – connect to the chassis ground of the system with a direct, low-inductance connection
5 S1 Low-voltage terminal of sense capacitor, C9. Also connects to the SENSE1A and SENSE1B pins of the IC
6 S2 Low-voltage terminal of sense capacitor, C8. Also connects to the SENSE2A and SENSE2B pins of the IC
(1) Pin positions of header J1 are designated right to left when viewed from the top side of the EVM.
(2) Working at an ESD-protected workstation, verify that any wrist straps, bootstraps or mats are connected and referencing the user to earth ground before power is applied to the EVM.
Table 2-2 J7 Header Connections
POSITION LABEL DESCRIPTION
1 VDD Connect a low-noise external source (8 V to 16 V) between the VDD and GND terminals
2 GND Connected by a trace on the PCB to GND
3 LDO Connect an external source (maximum 36 V) between the LDO and GND terminals to supply the on-board LDO that outputs a regulated 12 V to VDD
Table 2-3 J8 Header Connections
POSITION LABEL DESCRIPTION
1 ON Connected by a trace on the PCB to VDD
2 EN Jumper EN to ON or OFF to enable and disable the TPSF12C1, respectively
3 OFF Connected by a trace on the PCB to GND