8.3.1 DAC Architecture

For simplicity, a single resistor string is shown in Figure 26. This string consists of 4096 equal valued resistors with a switch at each junction of two resistors, plus a switch to ground. The code loaded into the DAC register determines which switch is closed, connecting the proper node to the amplifier. The input coding is straight binary with an ideal output voltage of:

D can take on any value between 0 and 4095. This configuration ensures that the DAC is monotonic.

Figure 26. DAC Resistor String

Because all eight DAC channels of the DAC128S085 can be controlled independently, each channel consists of a DAC register and a 12-bit DAC. Figure 27 is a simple block diagram of an individual channel in the DAC128S085. Depending on the mode of operation, data written into a DAC register causes the 12-bit DAC output to be updated, or an additional command is required to update the DAC output. Further description of the modes of operation can be found in Serial Interface.

Figure 27. Single-Channel Block Diagram

8.3.2 Output Amplifiers

The output amplifiers are rail-to-rail, providing an output voltage range of 0 V to V_A when the reference is V_A. All amplifiers, including rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0 V and V_A, in this case). For this reason, linearity is specified over less than the full output range of the DAC. However, if the reference is less than V_A, only the lowest codes experience a loss in linearity.

The output amplifiers can drive a load of 2 kΩ in parallel with 1500 pF to ground or to V_A. The zero-code and full-scale outputs for given load currents are available in the Electrical Characteristics.

8.3.3 Reference Voltage

The DAC128S085 uses dual external references, V_REF1 and V_REF2, which are shared by channels A, B, C, D and channels E, F, G, H, respectively. The reference pins are not buffered and have an input impedance of 30 kΩ. TI recommends driving V_REF1 and V_REF2 by voltage sources with low output impedance. The reference voltage range is 0.5 V to V_A, providing the widest possible output dynamic range.

8.3.4 Serial Interface

The three-wire interface is compatible with SPI, QSPI, and MICROWIRE, as well as most DSPs, and operates at clock rates up to 40 MHz. A valid serial frame contains 16 falling edges of SCLK. See Table 1 for information on a write sequence.

A write sequence begins by bringing the SYNC line low. Once SYNC is low, the data on the D_IN line is clocked into the 16-bit serial input register on the falling edges of SCLK. To avoid mis-clocking data into the shift register, it is critical that SYNC not be brought low on a falling edge of SCLK (see minimum and maximum setup times for SYNC in AC and Timing Characteristics and Figure 28). On the 16th falling edge of SCLK, the last data bit is clocked into the register. The write sequence is concluded by bringing the SYNC line high. Once SYNC is high, the programmed function (a change in the DAC channel address, mode of operation, or register contents) is executed. To avoid mis-clocking data into the shift register, it is critical that SYNC be brought high between the 16th and 17th falling edges of SCLK (see minimum and maximum hold times for SYNC in AC and Timing Characteristics and Figure 28).

Figure 28. CS Setup and Hold Times

If SYNC is brought high before the 15th falling edge of SCLK, the write sequence is aborted and the data that has been shifted into the input register is discarded. If SYNC is held low beyond the 17th falling edge of SCLK, the serial data presented at D_IN will begin to be output on D_OUT. More information on this mode of operation can be found in Daisy-Chain Operation. In either case, SYNC must be brought high for the minimum specified time before the next write sequence is initiated with a falling edge of SYNC.

Since the D_IN buffer draws more current when it is high, it should be idled low between write sequences to minimize power consumption. On the other hand, SYNC should be idled high to avoid the activation of daisy chain operation where D_OUT is active.

8.3.5 Daisy-Chain Operation

Daisy-chain operation allows communication with any number of DAC128S085s using a single serial interface. As long as the correct number of data bits are input in a write sequence (multiple of sixteen bits), a rising edge of SYNC will properly update all DACs in the system.

To support multiple devices in a daisy chain configuration, SCLK and SYNC are shared across all DAC128S085s and D_OUT of the first DAC in the chain is connected to D_IN of the second. Figure 29 shows three DAC128S085s connected in daisy chain fashion. Similar to a single channel write sequence, the conversion for a daisy chain operation begins on a falling edge of SYNC and ends on a rising edge of SYNC. A valid write sequence for n devices in a chain requires n times 16 falling edges to shift the entire input data stream through the chain. Daisy chain operation is ensured for a maximum SCLK speed of 30 MHz.

Figure 29. Daisy-Chain Configuration

The serial data output pin, D_OUT, is available on the DAC128S085 to allow daisy-chaining of multiple DAC128S085 devices in a system. In a write sequence, D_OUT remains low for the first 14 falling edges of SCLK before going high on the 15th falling edge. Subsequently, the next 16 falling edges of SCLK will output the first 16 data bits entered into D_IN. Figure 30 shows the timing of 3 DAC128S085s in Figure 29. In this instance, It takes 48 falling edges of SCLK followed by a rising edge of SYNC to load all three DAC128S085s with the appropriate register data. On the rising edge of SYNC, the programmed function is executed in each DAC128S085 simultaneously.

When connecting multiple devices in a daisy-chain configuration, it is important to note that the DAC128S085 will update the D_OUT signal on the falling edge of SCLK, and this will be sampled by the next DAC in the daisy chain on the next falling edge of the clock. Ensure that the timing requirements are met for proper operation. Specifically, pay attention to the data hold time after the SCLK falling (t_DH) requirement. Improper layout or loading may delay the clock signal between devices. If delayed to the point that data changes prior to meeting the hold time requirement, incorrect data can be sampled. If the clock delay cannot be resolved, an alternative solution is to add a delay between the D_OUT of one device and D_IN of the following device in the daisy chain. This increases the hold time margin and allows for correct sampling. Be aware though, that the tradeoff with this fix is that too much delay eventually impacts the setup time.

Figure 30. Daisy Chain Timing Diagram

8.3.6 DAC Input Data Update Mechanism

The DAC128S085 has two modes of operation, plus a few special command operations. The two modes of operation are Write Register Mode (WRM) and Write Through Mode (WTM). For the rest of this document, these modes will be referred to as WRM and WTM. The special command operations are separate from WRM and WTM because they can be called upon regardless of the current mode of operation. The mode of operation is controlled by the first four bits of the control register, DB15 through DB12. See Table 1 for a detailed summary.

When the DAC128S085 first powers up, the DAC is in WRM. In WRM, the registers of each individual DAC channel can be written to without updating the DAC outputs. This is accomplished by setting DB15 to 0, specifying the DAC register to be written to in DB[14:12], and entering the new DAC register setting in DB[11:0] (see Table 2). The DAC128S085 remains in WRM until the mode of operation is changed to WTM. The mode of operation is changed from WRM to WTM by setting DB[15:12] to 1001. Once in WTM, writing data to a DAC channel register causes the DAC output to be updated as well. Changing a DAC channel register in WTM is accomplished in the same manner as in WRM. However, in WTM the DAC register and output are updated at the completion of the command (see Table 2). Similarly, the DAC128S085 remains in WTM until the mode of operation is changed to WRM by setting DB[15:12] to 1000.

The special command operations can be exercised at any time regardless of the mode of operation. There are three special command operations. The first command is exercised by setting data bits DB[15:12] to 1010. This allows the user to update multiple DAC outputs simultaneously to the values currently loaded in their respective control registers. This command is valuable if the user wants each DAC output to be at a different output voltage, but still have all the DAC outputs changed to their appropriate values simultaneously (see Table 3).

The second special command allows the user to alter the DAC output of channel A with a single write frame. This command is exercised by setting data bits DB[15:12] to 1011 and data bits DB[11:0] to the desired control register value. This command also causes the DAC outputs of the other channels to update to their current control register values. The user may choose to exercise this command to save a write sequence. For example, the user may wish to update several DAC outputs simultaneously, including channel A. To accomplish this task in the minimum number of write frames, the user would alter the control register values of all the DAC channels except channel A while operating in WRM. The last write frame would be used to exercise the special command Channel A Write Mode. In addition to updating the control register of channel A and output to a new value, all of the other channels would be updated as well. At the end of this sequence of write frames, the DAC128S085 would still be operating in WRM (see Table 3).

The third special command allows the user to set all the DAC control registers and outputs to the same level. This command is commonly referred to as "broadcast" mode, as the same data bits are being broadcast to all of the channels simultaneously. This command is exercised by setting data bits DB[15:12] to 1100 and data bits DB[11:0] to the value that the user wishes to broadcast to all the DAC control registers. Once the command is exercised, each DAC output is updated by the new control register value. This command is frequently used to set all the DAC outputs to some known voltage such as 0 V, V_REF/2, or Full Scale. A summary of the commands can be found in Table 3.

8.3.7 Power-On Reset

The power-on reset circuit controls the output voltages of the eight DACs during power-up. Upon application of power, the DAC registers are filled with zeros and the output voltages are set to 0 V. The outputs remain at 0 V until a valid write sequence is made.

8.3.8 Transfer Characteristic

Figure 31. Input / Output Transfer Characteristic

8.4.1 Power-Down Modes

The DAC128S085 has three power-down modes, where different output terminations can be selected (see Table 4). With all channels powered down, the supply current drops to 0.1 µA at 3 V and 0.2 µA at 5 V. By selecting the channels to be powered down in DB[7:0] with a 1, individual channels can be powered down separately, or multiple channels can be powered down simultaneously. The three different output terminations include high output impedance, 100 kΩ to ground, and 2.5 kΩ to ground.

The output amplifiers, resistor strings, and other linear circuitry are all shut down in any of the power-down modes. The bias generator, however, is only shut down if all the channels are placed in power-down mode. The contents of the DAC registers are unaffected when in power-down. Therefore, each DAC register maintains its value prior to the DAC128S085 being powered down unless it is changed during the write sequence that instructed it to recover from power down. Minimum power consumption is achieved in the power-down mode with SYNC idled high, D_IN idled low, and SCLK disabled. The time to exit power-down (Wake-Up Time) is typically 3 µsec at 3 V and 20 µsec at 5 V.

8.5.1 Programming the DAC128S085

This section presents the step-by-step instructions for programming the serial input register.