SNLA132G October   2011  – November 2020 DS90UB928Q-Q1 , DS90UB941AS-Q1 , DS90UB948-Q1 , DS90UH925Q-Q1 , DS90UH926Q-Q1 , DS90UH940N-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Overview of Internal Test Pattern Generation
    1. 2.1 Color Mode
    2. 2.2 Video Timing Modes
    3. 2.3 Clock Generation
    4. 2.4 Pattern Selection
    5. 2.5 Pattern Inversion
    6. 2.6 Auto-Scrolling
  4. 3Serial Control Bus Registers for Internal Test Pattern Generation
    1. 3.1 Direct Register Map
      1. 3.1.1 Control and Configuration
      2. 3.1.2 Indirect Access Address and Data
      3. 3.1.3 DS90Ux928Q-Q1/DS90UB924-Q1 Internal Clock Source
    2. 3.2 Indirect Register Map
      1. 3.2.1 General Control
      2. 3.2.2 Internal Timing Control
      3. 3.2.3 Auto-Scrolling Control
  5. 4Configuration Examples
    1. 4.1 Auto-Scrolling Configuration
    2. 4.2 Internal Default Timing Configuration
    3. 4.3 Custom Display Configuration
    4. 4.4 1080p60 with External Clock Example Configuration
    5. 4.5 Resolution Readback Example
  6. 5Conclusion
  7. 6References
  8. 7Revision History

3.1.1 Control and Configuration

The PGCTL and PGCFG registers are used to enable and configure the general behavior of the pattern generator.

Table 3-1 Pattern Generator Direct Registers
ADD(hex) Register Name Bit Access Default (hex) Function Description
0x64 Pattern Generator Control
(PGCTL)		 7:4 RW 0x10 Pattern Generator Select Fixed Pattern Select
This field selects the pattern to output when in Fixed Pattern Mode. Scaled patterns are evenly distributed across the horizontal or vertical active regions. This field is ignored when Auto-Scrolling Mode is enabled. Table 3-4 shows the color selections in non-inverted followed by inverted color mode
0000: (Not available for 921/925Q/926Q) Checkerboard
0001: White/Black
0010: Black/White
0011: Red/Cyan
0100: Green/Magenta
0101: Blue/Yellow
0110: Horizontally Scaled Black to White/White to Black
0111: Horizontally Scaled Black to Red/Cyan to White
1000: Horizontally Scaled Black to Green/Magenta to White
1001: Horizontally Scaled Black to Blue/Yellow to White
1010: Vertically Scaled Black to White/White to Black
1011: Vertically Scaled Black to Red/Cyan to White
1100: Vertically Scaled Black to Green/Magenta to White
1101: Vertically Scaled Black to Blue/Yellow to White
1110: Custom color (or its inversion) configured in PGRS, PGGS, PGBS registers
1111: (927Q/928Q only) VCOM
3 Reserved
2 RW Color Bars Pattern (Not available for 921/925Q/926Q) Enable Color Bars Pattern
0: Color Bars Disabled (default)
1: Color Bars Enabled
Overrides the selection from bits [7:4]
1 RW VCOM Pattern Reverse (Not available for 921/925Q/926Q) Reverse Order of Color Bands in VCOM Pattern
0: Color sequence from top left is (YCBR) (default)
1: Color sequence from top left is (RBCY)
0 RW Pattern Generator Enable Pattern Generator Enable
1: Enable Pattern Generator (1)
0: Disable Pattern Generator
0x65 Pattern Generator Configuration
(PGCFG)		 7 0x00 Reserved
6 RW Checkerboard Scale (Not available for 921/925Q/926Q) Scale Checkerboard Patterns
0: Normal operation (each square is 1x1 pixel) (default)
1: Scale Checkerboard Patterns (VCOM and Checkerboard) by 8 (each square is 8x8 pixels)
Setting this bit gives better visibility of the checkerboard patterns
5 RW Custom Checkerboard (Not available for 921/925Q/926Q) Use Custom Color in Checkerboard Pattern
0: Use white and black Checkerboard pattern (default)
1: Use the Customer Color and Black in the Checkerboard Pattern
4 RW Pattern Generator 18 Bits 18-bit Mode Select
1: Enable 18-bit color pattern generation. Scaled patterns have 64 levels of brightness and the R, G, and B outputs use the six most significant color bits.
0: Enable 24-bit pattern generation. Scaled patterns use 256 levels of brightness.
3 RW Pattern Generator External Clock Select External Clock Source
1: Selects the external pixel clock when using internal timing.
0: Selects the internal divided clock when using internal timing This bit has no effect in external timing mode (PATGEN_TSEL = 0).
2 RW Pattern Generator Timing Select Timing Select Control
1: The pattern generator creates its own video timing as configured in the Pattern Generator Total Frame Size, Active Frame Size. Horizontal Sync Width, Vertical Sync Width, Horizontal Back Porch, Vertical Back Porch, and Sync Configuration registers.
0: The pattern generator uses external video timing from the pixel clock, Data Enable, Horizontal Sync, and Vertical Sync signals.
1 RW Pattern Generator Color Invert Enable Inverted Color Patterns
1: Invert the color output.
0: Do not invert the color output.
0 RW Pattern Generator Auto- Scroll Enable Auto-Scroll Enable:
1: The pattern generator automatically moves to the next enabled pattern after the number of frames specified in the Pattern Generator Frame Time Register (PGFT).
0: The pattern generator retains the current pattern.
0x68 Pattern Generator Debug
(PGDBG)
948 and 940/940N only		 7:4 RW 0x00 PATGEN Debug Select Test Mux Select: This field selects the signals to be monitored in the PGTSTDAT register. These signals can be monitored while the serializer is in PATGEN mode, or during normal operation as well. Bit 3 of this register must be set high to enable the test mux.
0000: Video Active Height LSB [5:0]
0001: Video Active Height MSB [11:6]
0010: Video Active Width LSB [5:0]
0011: Video Active Width MSB [11:6]
3 RW PATGEN BIST Enable Pattern Generator BIST Enable: Enables Pattern Generator in BIST mode. Pattern Generator will compare received video data with local generated pattern. Upstream device must be programmed to the same pattern. PATGEN enable in register 0x64 should not be set prior to enabling this bit.
2 RW RESERVED
1 RW RESERVED
0 RW PATGEN Debug Sample Triggers a sampling of the data for the selected test mux. This bit must be set before reading back the test data from PGTSTDAT. This bit is self clearing
0x69 Pattern Generator Test Data
(PGTSTDAT)
948 and 940/940N only		 7 R 0x00 Pattern Generator BIST Error Pattern Generator BIST Error Flag During Pattern Generator BIST mode, this bit indicates if the BIST engine has detected errors. If the BIST Error Count (available in the Pattern Generator indirect registers) is non-zero, this flag will be set.
6 R RESERVED
5:0 R Pattern Generator Test Data Test Data: This field contains data output based on the selection of the test mux in PGDBG. The PATGEN debug sample bit in PGDBG must be set high to trigger an update to this data.
(1) PATGEN at the deserializer side should only be enabled via local I2C, not via remote control from the serializer. Enabling PATGEN remotely from the serializer side will cause a loss of I2C communication over the bidirectional control channel.